Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration - Imana, Jose L.; Pinuel, Luis; Kuo, Yao-Ming; Ruano, Oscar; Garcia-Herrero, Francisco (IEEE transactions on circuits and systems. II, Express briefs, 2024)
Keywords: Arithmetic; Binary codes; Computer architecture; cryptography; Digital signal processing; Error correcting codes; Error correction; Fields (mathematics); finite field arithmetic; Hamming weight; Hardware; Mathematical analysis; Matrix decomposition; Multiplication; Multiplication & division; Multipliers; NIST; NIST trinomials; Polynomials; RISC; RISC-V; Shift registers