Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 71; no. 8; pp. 3915 - 3919
• Main Authors: Imana, Jose L., Pinuel, Luis, Kuo, Yao-Ming, Ruano, Oscar, Garcia-Herrero, Francisco
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Arithmetic; Binary codes; Computer architecture; cryptography; Digital signal processing; Error correcting codes; Error correction; Fields (mathematics); finite field arithmetic; Hamming weight; Hardware; Mathematical analysis; Matrix decomposition; Multiplication; Multiplication & division; Multipliers; NIST; NIST trinomials; Polynomials; RISC; RISC-V; Shift registers
• ISSN: 1549-7747; 1558-3791; 1558-3791
• DOI: 10.1109/TCSII.2024.3369103

Binary extension field arithmetic is widely used in several important applications such as error-correcting codes, cryptography and digital signal processing. Multiplication is usually considered the most important finite field arithmetic operation. Therefore efficient hardware architectures for multiplication are highly desired. In this brief, a new architecture for multiplication over finite fields generated by irreducible trinomials <inline-formula> <tex-math notation="LaTeX">f(x) = x^{m}+x^{t}+1 </tex-math></inline-formula> is presented. The architecture here proposed is based on the use of a polynomial multiplier and a cyclic shift register that can perform the multiplication in <inline-formula> <tex-math notation="LaTeX">t-1 </tex-math></inline-formula> clock cycles. The general architecture is applied to the trinomials recommended by NIST (National Institute of Standards and Technology). Furthermore, a RISC-V instruction set for the proposed multiplier is implemented and validated using VeeR-EL2 on a Nexys A7 FPGA. To the best knowledge of the authors, this is the first work that integrates the multiplication based on NIST trinomials into a RISC-V SoC. Results show an improvement of several orders of magnitude in terms of latency at a cost of less than 50% more of area.