APA (7th ed.) Citation

Imana, J. L., Pinuel, L., Kuo, Y., Ruano, O., & Garcia-Herrero, F. (2024). Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration. IEEE transactions on circuits and systems. II, Express briefs, 71(8), 3915-3919. https://doi.org/10.1109/TCSII.2024.3369103

Chicago Style (17th ed.) Citation

Imana, Jose L., Luis Pinuel, Yao-Ming Kuo, Oscar Ruano, and Francisco Garcia-Herrero. "Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration." IEEE Transactions on Circuits and Systems. II, Express Briefs 71, no. 8 (2024): 3915-3919. https://doi.org/10.1109/TCSII.2024.3369103.

MLA (9th ed.) Citation

Imana, Jose L., et al. "Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration." IEEE Transactions on Circuits and Systems. II, Express Briefs, vol. 71, no. 8, 2024, pp. 3915-3919, https://doi.org/10.1109/TCSII.2024.3369103.