Artificial Neural Network-Based Compact Modeling Methodology for Advanced Transistors

The artificial neural network (ANN)-based compact modeling methodology is evaluated in the context of advanced field-effect transistor (FET) modeling for Design-Technology-Cooptimization (DTCO) and pathfinding activities. An ANN model architecture for FETs is introduced, and the results clearly show...

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Published inIEEE transactions on electron devices Vol. 68; no. 3; pp. 1318 - 1325
Main Authors Wang, Jing, Kim, Yo-Han, Ryu, Jisu, Jeong, Changwook, Choi, Woosung, Kim, Daesin
Format Journal Article
LanguageEnglish
Published New York IEEE 01.03.2021
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
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ISSN0018-9383
1557-9646
DOI10.1109/TED.2020.3048918

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Abstract The artificial neural network (ANN)-based compact modeling methodology is evaluated in the context of advanced field-effect transistor (FET) modeling for Design-Technology-Cooptimization (DTCO) and pathfinding activities. An ANN model architecture for FETs is introduced, and the results clearly show that by carefully choosing the conversion functions (i.e., from ANN outputs to device terminal currents or charges) and the loss functions for ANN training, ANN models can reproduce the current-voltage and charge-voltage characteristics of advanced FETs with excellent accuracy. A few key techniques are introduced in this work to enhance the capabilities of ANN models (e.g., model retargeting, variability modeling) and to improve ANN training efficiency and SPICE simulation turn-around-time (TAT). A systematical study on the impact of the ANN size on ANN model accuracy and SPICE simulation TAT is conducted, and an automated flow for generating optimum ANN models is proposed. The findings in this work suggest that the ANN-based methodology can be a promising compact modeling solution for advanced DTCO and pathfinding activities.
AbstractList The artificial neural network (ANN)-based compact modeling methodology is evaluated in the context of advanced field-effect transistor (FET) modeling for Design-Technology-Cooptimization (DTCO) and pathfinding activities. An ANN model architecture for FETs is introduced, and the results clearly show that by carefully choosing the conversion functions (i.e., from ANN outputs to device terminal currents or charges) and the loss functions for ANN training, ANN models can reproduce the current-voltage and charge-voltage characteristics of advanced FETs with excellent accuracy. A few key techniques are introduced in this work to enhance the capabilities of ANN models (e.g., model retargeting, variability modeling) and to improve ANN training efficiency and SPICE simulation turn-around-time (TAT). A systematical study on the impact of the ANN size on ANN model accuracy and SPICE simulation TAT is conducted, and an automated flow for generating optimum ANN models is proposed. The findings in this work suggest that the ANN-based methodology can be a promising compact modeling solution for advanced DTCO and pathfinding activities.
Author Jeong, Changwook
Wang, Jing
Ryu, Jisu
Kim, Daesin
Kim, Yo-Han
Choi, Woosung
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SubjectTerms Artificial neural network (ANN)
Artificial neural networks
circuit simulation
compact modeling
Data models
design-technology-cooptimization (DTCO)
Electric potential
emerging devices
Field effect transistors
field-effect transistor (FET)
Integrated circuit modeling
machine learning
Mathematical model
Methodology
Model accuracy
Modelling
Neural networks
pathfinding
Semiconductor device modeling
Semiconductor devices
SPICE
statistical modeling
Training
Voltage
Title Artificial Neural Network-Based Compact Modeling Methodology for Advanced Transistors
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