SOT-MRAM Digital PIM Architecture With Extended Parallelism in Matrix Multiplication

• Published in: IEEE transactions on computers Vol. 71; no. 11; pp. 2816 - 2828
• Main Authors: Kim, Taehwan, Jang, Yunho, Kang, Min-Gu, Park, Byong-Guk, Lee, Kyung-Jin, Park, Jongsun
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog to digital converters; CNN Accelerator; Computational efficiency; Computer architecture; Copying; digital processing in-memory; Errors; Hardware; In-memory computing; Logic gates; Magnetic anisotropy; Magnetic tunneling; Memory management; Multiplication; Parallel processing; Parameters; Performance evaluation; Pipelining (computers); Random access memory; Spintronics; Switches; Throughput; VCMA effect
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/TC.2022.3155277

Emerging device-based digital processing-in-memory (PIM) architectures have been actively studied due to their energy and area efficiency derived from analog to digital converter (ADC)-less PIM hardware. However, digital PIM architectures generally need large extra memories to copy parameters, and they also suffer from low computation per memory-cycle efficiencies. In this paper, we present a novel spin-orbit torque magnetic random access memory (SOT-MRAM) based digital PIM architecture to alleviate the extra memory size burden and computation cycle issues. First, we propose the spintronics-assisted logic-in-memory (SLIM) cells to support efficient digital logic operations inside memories, where the voltage-controlled magnetic anisotropy (VCMA) is exploited to enhance the computation per memory-cycle efficiencies. In addition, crossed input source PIM (CRISP) architecture is proposed to extend the merits of SLIM cells by eliminating the extra memories for parameter copying while significantly improving the degree of parallel processing. An intra-memory pipelining scheme is also considered to further increase the throughput of CRISP. The proposed CRISP architecture has been implemented using 28 nm CMOS process, and it presents 1.10 TOPS/W and 0.95 TOPS/mm 2 , showing considerable improvements of energy efficiency and throughput per area, compared to the state-of-the-art digital PIM architecture. Finally, to evaluate the impact of computation errors induced from the SOT devices and circuits in CRISP architecture, classification accuracy simulations have been performed while applying computation errors.