Floorplan-aware application-specific network-on-chip topology synthesis using genetic algorithm technique
Communication plays a critical role in the design and performance of multi-core systems-on-chip (SoCs). Networks-on-chip (NoCs) have been proposed as a promising solution to complex on-chip communication problems. As regular NoC topologies are infeasible to satisfy the performance demand for applica...
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| Published in | The Journal of supercomputing Vol. 61; no. 3; pp. 418 - 437 |
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| Main Authors | , |
| Format | Journal Article |
| Language | English |
| Published |
Boston
Springer US
01.09.2012
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| Subjects | |
| Online Access | Get full text |
| ISSN | 0920-8542 1573-0484 |
| DOI | 10.1007/s11227-011-0599-z |
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| Abstract | Communication plays a critical role in the design and performance of multi-core systems-on-chip (SoCs). Networks-on-chip (NoCs) have been proposed as a promising solution to complex on-chip communication problems. As regular NoC topologies are infeasible to satisfy the performance demand for application-specific NoC, customized topology synthesis is therefore desirable. However, NoC topology synthesis problem is an NP-hard problem. In this paper, we propose a suboptimal genetic-algorithm based technique to synthesize application-specific NoC topology with system-level floorplan awareness. The method minimizes the power consumption and router resources while satisfying latency and bandwidth performance constraints. We have evaluated the proposed technique by running a number of representative benchmark applications and the results indicate that our method generates approximate optimal topologies effectively and efficiently for all benchmarks under consideration. |
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| AbstractList | Communication plays a critical role in the design and performance of multi-core systems-on-chip (SoCs). Networks-on-chip (NoCs) have been proposed as a promising solution to complex on-chip communication problems. As regular NoC topologies are infeasible to satisfy the performance demand for application-specific NoC, customized topology synthesis is therefore desirable. However, NoC topology synthesis problem is an NP-hard problem. In this paper, we propose a suboptimal genetic-algorithm based technique to synthesize application-specific NoC topology with system-level floorplan awareness. The method minimizes the power consumption and router resources while satisfying latency and bandwidth performance constraints. We have evaluated the proposed technique by running a number of representative benchmark applications and the results indicate that our method generates approximate optimal topologies effectively and efficiently for all benchmarks under consideration. |
| Author | Lai, G. Lin, X. |
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| Cites_doi | 10.1109/TVLSI.2003.817546 10.1109/ICCAD.2005.1560070 10.1109/TVLSI.2006.878263 10.1016/j.micpro.2010.01.001 10.1109/TVLSI.2006.871762 10.1109/TCAD.2008.2010691 10.1007/s00453-001-0038-2 10.1109/TVLSI.2008.2011205 10.1109/TVLSI.2008.2004592 10.1109/DATE.2004.1269002 10.1109/DATE.2004.1268999 10.1145/966747.966758 10.1007/s11227-009-0376-4 10.1016/j.vlsi.2007.12.002 |
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| Keywords | Topology synthesis Application-specific NoC Network-on-chip (NoC) Genetic algorithms |
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| Title | Floorplan-aware application-specific network-on-chip topology synthesis using genetic algorithm technique |
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