Floorplan-aware application-specific network-on-chip topology synthesis using genetic algorithm technique

• Published in: The Journal of supercomputing Vol. 61; no. 3; pp. 418 - 437
• Main Authors: Lai, G., Lin, X.
• Format: Journal Article
• Language: English
• Published: Boston Springer US 01.09.2012
• Subjects: Compilers; Computer Science; Interpreters; Processor Architectures; Programming Languages; Topology synthesis; Application-specific NoC; Network-on-chip (NoC); Genetic algorithms
• ISSN: 0920-8542; 1573-0484
• DOI: 10.1007/s11227-011-0599-z

Communication plays a critical role in the design and performance of multi-core systems-on-chip (SoCs). Networks-on-chip (NoCs) have been proposed as a promising solution to complex on-chip communication problems. As regular NoC topologies are infeasible to satisfy the performance demand for application-specific NoC, customized topology synthesis is therefore desirable. However, NoC topology synthesis problem is an NP-hard problem. In this paper, we propose a suboptimal genetic-algorithm based technique to synthesize application-specific NoC topology with system-level floorplan awareness. The method minimizes the power consumption and router resources while satisfying latency and bandwidth performance constraints. We have evaluated the proposed technique by running a number of representative benchmark applications and the results indicate that our method generates approximate optimal topologies effectively and efficiently for all benchmarks under consideration.