APA (7th ed.) Citation

Lai, G., & Lin, X. (2012). Floorplan-aware application-specific network-on-chip topology synthesis using genetic algorithm technique. The Journal of supercomputing, 61(3), 418-437. https://doi.org/10.1007/s11227-011-0599-z

Chicago Style (17th ed.) Citation

Lai, G., and X. Lin. "Floorplan-aware Application-specific Network-on-chip Topology Synthesis Using Genetic Algorithm Technique." The Journal of Supercomputing 61, no. 3 (2012): 418-437. https://doi.org/10.1007/s11227-011-0599-z.

MLA (9th ed.) Citation

Lai, G., and X. Lin. "Floorplan-aware Application-specific Network-on-chip Topology Synthesis Using Genetic Algorithm Technique." The Journal of Supercomputing, vol. 61, no. 3, 2012, pp. 418-437, https://doi.org/10.1007/s11227-011-0599-z.