Interval graph algorithms for two-dimensional multiple folding of array-based VLSI layouts
Folding or topological compaction of array-based VLSI layouts is an important optimization step that is carried out after logic synthesis. In this paper, a new approach to two-dimensional multiple folding of array-based VLSI layouts is presented. From the specification of the problem a pair of inter...
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| Published in | IEEE transactions on computer-aided design of integrated circuits and systems Vol. 13; no. 10; pp. 1201 - 1222 |
|---|---|
| Main Authors | , |
| Format | Journal Article |
| Language | English |
| Published |
New York, NY
IEEE
1994
Institute of Electrical and Electronics Engineers |
| Subjects | |
| Online Access | Get full text |
| ISSN | 0278-0070 |
| DOI | 10.1109/43.317463 |
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| Abstract | Folding or topological compaction of array-based VLSI layouts is an important optimization step that is carried out after logic synthesis. In this paper, a new approach to two-dimensional multiple folding of array-based VLSI layouts is presented. From the specification of the problem a pair of intersection graphs is created. We show that any pair of interval graphs that contain the intersection graphs as spanning subgraphs corresponds to a set of feasible foldings. Next, a complete and exact characterization of the folding problem is presented. In particular, it is shown that the set of all feasible foldings associated with a given pair of interval graphs corresponds to the set of independent colorings of a pair of compatibility graphs. The compatibility graphs are derived from a pair of interval graphs that contain the intersection graphs as spanning subgraphs. Thus, minimizing the area of a layout is tantamount to finding a pair of compatibility graphs such that the product of their chromatic numbers is minimum. As important as minimizing the area of a layout is, the ability to rapidly generate compact layouts over a wide range of aspect ratios is often equally, if not more, important. The interval graph-based formulation of the folding problem permits a controlled and systematic generation of compact layouts with varying aspect ratios. Efficient and provably correct algorithms to generate compact layouts that have a given number of rows or a given number of columns within their minimum and maximum possible values are given. The basic theory and methods are extended to include I/O and other types of constraints. Finally, the results of experiments that were carried out on a large number of benchmark problems are given. These results are compared with those obtained by previously reported methods.< > |
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| AbstractList | Folding or topological compaction of array based VLSI layouts is an important optimization step that is executed after logic synthesis. A new approach to two dimensional multiple folding of array-based VLSI layouts is presented. The interval graph formulation makes it possible to capture the interrelationship between column and row foldings in a pair of compatibility graphs. With the use of the technique presented, minimization of the area and control of the aspect ratio can be achieved. Folding or topological compaction of array-based VLSI layouts is an important optimization step that is carried out after logic synthesis. In this paper, a new approach to two-dimensional multiple folding of array-based VLSI layouts is presented. From the specification of the problem a pair of intersection graphs is created. We show that any pair of interval graphs that contain the intersection graphs as spanning subgraphs corresponds to a set of feasible foldings. Next, a complete and exact characterization of the folding problem is presented. In particular, it is shown that the set of all feasible foldings associated with a given pair of interval graphs corresponds to the set of independent colorings of a pair of compatibility graphs. The compatibility graphs are derived from a pair of interval graphs that contain the intersection graphs as spanning subgraphs. Thus, minimizing the area of a layout is tantamount to finding a pair of compatibility graphs such that the product of their chromatic numbers is minimum. As important as minimizing the area of a layout is, the ability to rapidly generate compact layouts over a wide range of aspect ratios is often equally, if not more, important. The interval graph-based formulation of the folding problem permits a controlled and systematic generation of compact layouts with varying aspect ratios. Efficient and provably correct algorithms to generate compact layouts that have a given number of rows or a given number of columns within their minimum and maximum possible values are given. The basic theory and methods are extended to include I/O and other types of constraints. Finally, the results of experiments that were carried out on a large number of benchmark problems are given. These results are compared with those obtained by previously reported methods.< > |
| Author | Ho, K.C. Vrudhula, S.B.K. |
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| Keywords | Logic circuit Interval graph VLSI circuit Integrated circuit Optimization method Theoretical study Compaction Algorithm Computer aided design |
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| References | ref2s ref20s ref6s ref11s golumbic (ref5s) 1980 ref3s ref21s ref4s kashiwabara (ref13s) 1979 kashiwabara (ref14s) 1979 micheli (ref16s) 1983; cad 2 brayton (ref1) 1984 ho (ref9s) 1993 ho (ref10s) 1993 ref12s ref7s ref15s ref8s ref17s ref19s aho (ref1s) 1983 ref18s |
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| Snippet | Folding or topological compaction of array-based VLSI layouts is an important optimization step that is carried out after logic synthesis. In this paper, a new... Folding or topological compaction of array based VLSI layouts is an important optimization step that is executed after logic synthesis. A new approach to two... |
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| SubjectTerms | Applied sciences Compaction Constraint theory Control systems Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Integrated circuits Logic arrays Programmable logic arrays Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Very large scale integration |
| Title | Interval graph algorithms for two-dimensional multiple folding of array-based VLSI layouts |
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