A Systolic Array-Based FPGA Parallel Architecture for the BLAST Algorithm
A design of systolic array-based Field Programmable Gate Array (FPGA) parallel architecture for Basic Local Alignment Search Tool (BLAST) Algorithm is proposed. BLAST is a heuristic biological sequence alignment algorithm which has been used by bioinformatics experts. In contrast to other designs th...
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| Published in | ISRN Bioinformatics Vol. 2012; no. 2012; pp. 1 - 11 |
|---|---|
| Main Authors | , , |
| Format | Journal Article |
| Language | English |
| Published |
Cairo, Egypt
Hindawi Puplishing Corporation
2012
International Scholarly Research Network |
| Online Access | Get full text |
| ISSN | 2090-7346 2090-7338 2090-7346 |
| DOI | 10.5402/2012/195658 |
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| Abstract | A design of systolic array-based Field Programmable Gate Array (FPGA) parallel architecture for Basic Local Alignment Search Tool (BLAST) Algorithm is proposed. BLAST is a heuristic biological sequence alignment algorithm which has been used by bioinformatics experts. In contrast to other designs that detect at most one hit in one-clock-cycle, our design applies a Multiple Hits Detection Module which is a pipelining systolic array to search multiple hits in a single-clock-cycle. Further, we designed a Hits Combination Block which combines overlapping hits from systolic array into one hit. These implementations completed the first and second step of BLAST architecture and achieved significant speedup comparing with previously published architectures. |
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| AbstractList | A design of systolic array-based Field Programmable Gate Array (FPGA) parallel architecture for Basic Local Alignment Search Tool (BLAST) Algorithm is proposed. BLAST is a heuristic biological sequence alignment algorithm which has been used by bioinformatics experts. In contrast to other designs that detect at most one hit in one-clock-cycle, our design applies a Multiple Hits Detection Module which is a pipelining systolic array to search multiple hits in a single-clock-cycle. Further, we designed a Hits Combination Block which combines overlapping hits from systolic array into one hit. These implementations completed the first and second step of BLAST architecture and achieved significant speedup comparing with previously published architectures. |
| Author | Devabhaktuni, Vijay Wang, Hong Guo, Xinyu |
| AuthorAffiliation | 1 Electrical Engineering and Computer Science Department, The University of Toledo, MS.308, 2801 W. Bancroft Street, Toledo, OH 43607, USA 2 Department of Engineering Technology, The University of Toledo, MS.402, 2801 W. Bancroft Street, Toledo, OH 43606, USA |
| AuthorAffiliation_xml | – name: 2 Department of Engineering Technology, The University of Toledo, MS.402, 2801 W. Bancroft Street, Toledo, OH 43606, USA – name: 1 Electrical Engineering and Computer Science Department, The University of Toledo, MS.308, 2801 W. Bancroft Street, Toledo, OH 43607, USA |
| Author_xml | – sequence: 1 fullname: Guo, Xinyu – sequence: 2 fullname: Wang, Hong – sequence: 3 fullname: Devabhaktuni, Vijay |
| BackLink | https://www.ncbi.nlm.nih.gov/pubmed/25969747$$D View this record in MEDLINE/PubMed |
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| Cites_doi | 10.1016/j.parco.2007.09.003 10.1007/978-3-540-70600-7_4 10.1093/nar/14.1.159 10.1007/s11265-007-0073-6 10.1093/nar/25.17.3389 10.1093/bioinformatics/18.3.440 10.1109/2.375174 10.1016/0022-2836(81)90087-5 10.1007/s11265-007-0069-2 10.1016/0022-2836(70)90057-4 10.1006/jmbi.1990.9999 |
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| Copyright | Copyright © 2012 Xinyu Guo et al. Copyright © 2012 Xinyu Guo et al. 2012 |
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| Title | A Systolic Array-Based FPGA Parallel Architecture for the BLAST Algorithm |
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