An improved exploration–exploitation mechanism of reptile search algorithm for quadrature mirror filter bank design and its FPGA implementation

• Published in: Analog integrated circuits and signal processing Vol. 125; no. 2; p. 39
• Main Authors: Aich, Raina Modak, Dhabal, Supriya, Venkateswaran, Palaniandavar
• Format: Journal Article
• Language: English
• Published: New York Springer US 01.11.2025; Springer Nature B.V
• Subjects: Algorithms; Amplitudes; Circuits and Systems; Design; Distortion; Electrical Engineering; Engineering; Errors; Evolutionary computation; Exploitation; Field programmable gate arrays; Filter banks; Objective function; Optimization algorithms; Optimization techniques; Power consumption; Quadratures; Reconstruction; Reptiles; Search algorithms; Signal processing; Signal,Image and Speech Processing; Spartan 6; Virtex 5; Kintex 7; QMF; Reptile Search Algorithm; FPGA
• ISSN: 0925-1030; 1573-1979
• DOI: 10.1007/s10470-025-02495-w

This paper presents an enhanced version of the Reptile Search Algorithm (RSA) based on the Differential Evolution (DE). In the proposed RSADE algorithm, the exploration and exploitation phases of RSA are enriched by the DE mutation phase. This is done to avoid trapping solutions into both global and local minima. The proposed algorithm is used to design a Near-Perfect Reconstruction (NPR) Quadrature Mirror Filter (QMF) bank. A minimized closed-form objective function is constructed by combining the values of pass-band ripple, amplitude distortion, transition-band error, and stop-band error. Initially, a test on standard IEEE CEC 2014 benchmark functions is performed, where the RSADE algorithm obtains rank 1. Compared to the current cutting-edge algorithms, the proposed algorithm exhibits a 26.79% increase in stop-band attenuation, 90.90%, 80.39%, 75.59%, 75.85%, and 67.10% decrease in transition-band error, stop-band error, pass-band error, overall amplitude distortion, and peak reconstruction error, respectively. Further, the proposed design is simulated with the Xilinx ISE Design Suite and executed on three Field Programmable Gate Array (FPGA) platforms using Spartan 6, Virtex 5, and Kintex 7 for filter tap 32. For instance, the average improvements in Spartan 6 compared to some recent algorithms are 4.75%, 6.78%, 5.07%, and 0.06% in the number of slice LUTs, occupied slices, fully used LUT-FF pairs, and total power consumption, respectively. The experimental outcomes of the proposed algorithm show its improvement in solving complex multimodal problems compared to the existing state-of-the-art algorithms.