Parallel design of SFO optimization algorithm based on FPGA
Taking a lot of time to solve optimization problems has become a challenge for metaheuristic algorithms. Due to independence of the metaheuristics components, parallel processing is a good option to reduce the computational time and to find high quality solutions that are close to the optimum with a...
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| Published in | The Journal of supercomputing Vol. 80; no. 8; pp. 10796 - 10817 |
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| Main Authors | , , , |
| Format | Journal Article |
| Language | English |
| Published |
New York
Springer US
01.05.2024
Springer Nature B.V |
| Subjects | |
| Online Access | Get full text |
| ISSN | 0920-8542 1573-0484 |
| DOI | 10.1007/s11227-023-05851-7 |
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| Abstract | Taking a lot of time to solve optimization problems has become a challenge for metaheuristic algorithms. Due to independence of the metaheuristics components, parallel processing is a good option to reduce the computational time and to find high quality solutions that are close to the optimum with an acceptable cost. One of these metaheuristic algorithms is the Sailfish Optimizer (SFO) which is inspired by a group of hunting sailfish. The SFO algorithm uses a simple method to provide a dynamic balance between exploration and exploitation phases, creates a swarm diversity, avoids local optima, and guarantees high convergence speed. It has been shown that the SFO algorithm outperforms various state-of-art metaheuristic algorithms for multimodal and high dimensional benchmark functions and complicated real-world optimization problems in terms of accuracy and speed by CPU and GPU implementation. In this paper, to speedup this algorithm and increase its performance we propose a reconfigurable hardware version of SFO implemented on Field Programmable Gate Array (FPGA). The FPGA-based SFO can be a very good option in many applications with massive calculations. Due to the inherent parallelism and high computing capabilities of FPGA, the SFO algorithm gains optimum computational time despite the complexity of optimization problems. We have compared the performance of the proposed FPGA-based SFO with its CPU and GPU implementation and some other metaheuristic algorithms. The results show the FPGA implementation is considerably faster than the CPU and GPU implementation. Also, it outperforms other compared FPGA-based metaheuristic algorithms in terms of execution time and convergence speed. |
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| AbstractList | Taking a lot of time to solve optimization problems has become a challenge for metaheuristic algorithms. Due to independence of the metaheuristics components, parallel processing is a good option to reduce the computational time and to find high quality solutions that are close to the optimum with an acceptable cost. One of these metaheuristic algorithms is the Sailfish Optimizer (SFO) which is inspired by a group of hunting sailfish. The SFO algorithm uses a simple method to provide a dynamic balance between exploration and exploitation phases, creates a swarm diversity, avoids local optima, and guarantees high convergence speed. It has been shown that the SFO algorithm outperforms various state-of-art metaheuristic algorithms for multimodal and high dimensional benchmark functions and complicated real-world optimization problems in terms of accuracy and speed by CPU and GPU implementation. In this paper, to speedup this algorithm and increase its performance we propose a reconfigurable hardware version of SFO implemented on Field Programmable Gate Array (FPGA). The FPGA-based SFO can be a very good option in many applications with massive calculations. Due to the inherent parallelism and high computing capabilities of FPGA, the SFO algorithm gains optimum computational time despite the complexity of optimization problems. We have compared the performance of the proposed FPGA-based SFO with its CPU and GPU implementation and some other metaheuristic algorithms. The results show the FPGA implementation is considerably faster than the CPU and GPU implementation. Also, it outperforms other compared FPGA-based metaheuristic algorithms in terms of execution time and convergence speed. |
| Author | Naji, Hamid Reza Momeni, Hossien Shadravan, Soodeh Jafarabadi, Hossien Mousa |
| Author_xml | – sequence: 1 givenname: Hamid Reza surname: Naji fullname: Naji, Hamid Reza email: naji@kgut.ac.ir organization: Department of Computer Engineering and Information Technology, Graduate University of Advanced Technology – sequence: 2 givenname: Soodeh surname: Shadravan fullname: Shadravan, Soodeh organization: Department of Computer Engineering, Islamic Azad University – sequence: 3 givenname: Hossien Mousa surname: Jafarabadi fullname: Jafarabadi, Hossien Mousa organization: Department of Mathematics, Islamic Azad University – sequence: 4 givenname: Hossien surname: Momeni fullname: Momeni, Hossien organization: Department of Computer Engineering and Information Technology, Graduate University of Advanced Technology |
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| ContentType | Journal Article |
| Copyright | The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2024. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2024. |
| Copyright_xml | – notice: The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2024. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. – notice: The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2024. |
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| Keywords | Field programmable gate array Parallel programming SFO algorithm Metaheuristic algorithm Finite state machine |
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ShadravanSNajiHRBardsiriVKThe sailfish optimizer: a novel nature-inspired metaheuristic algorithm for solving constrained engineering optimization problemEng Appl Artif Intell201980203410.1016/j.engappai.2019.01.001 HashimFAHenry gas solubility optimization: a novel physics-based algorithmFutur Gener Comput Syst201910164666710.1016/j.future.2019.07.015 SaremiSMirjaliliSLewisAGrasshopper optimisation algorithm: theory and applicationAdv Eng Softw20171105304710.1016/j.advengsoft.2017.01.004 Zou, X., Wang, L., Tang, Y. et al. 2018. Parallel design of intelligent optimization algorithm based on FPGA. Int J Adv Manuf Technol, Springer, Vol 94, pp. 3399–3412. Panda, A. K., Rajput, P., & Shukla, B. 2012. FPGA implementation of 8, 16 and 32 bit LFSR with maximum length feedback polynomial using VHDL. In: 2012 International Conference on Communication Systems and Network Technologies (pp. 769–773). IEEE. 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| References_xml | – reference: Mohammadi-BalaniANayeriMDAzarATaghizadeh-YazdiMGolden eagle optimizer: a nature-inspired metaheuristic algorithmComput Ind Eng2021115210705010.1016/j.cie.2020.107050 – reference: KumarMKulkarniAJSatapathySCSocio evolution & learning optimization algorithm: a socio-inspired optimization methodologyFutur Gener Comput Syst201818125227210.1016/j.future.2017.10.052 – reference: Panda, A. K., Rajput, P., & Shukla, B. 2012. FPGA implementation of 8, 16 and 32 bit LFSR with maximum length feedback polynomial using VHDL. In: 2012 International Conference on Communication Systems and Network Technologies (pp. 769–773). IEEE. – reference: CheraghalipourAHajiaghaei-KeshteliMPaydarMMTree growth algorithm (TGA): a novel approach for solving optimization problemsEng Appl Artif Intell201817239341410.1016/j.engappai.2018.04.021 – reference: AnisSAFPGA implementation of parallel particle swarm optimization algorithm and compared with genetic algorithmInt J Adv Comput Sci Appl2016175764 – reference: Abdoalnasir A., Psarakis M., Dounis A. 2018 An efficient FPGA implementation of the big bang-big crunch optimization algorithm. ARC 2018. Lecture notes in computer science, Springer, vol 10824, pp 166-177. – reference: Suganthan, P.N. et al., 2005. Problem definitions and evaluation criteria for the CEC 2005 special session on RealParameter optimization, KanGAL report 2005005. – reference: CalazanRMNadiaNMourelleLMA hardware accelerator for particle swarm optimizationAppl Soft Comput20141434735610.1016/j.asoc.2012.12.034 – reference: HollandJHGenetic algorithmsSci Am1992267667210.1038/scientificamerican0792-66 – reference: AmeurMSBSaklyAFPGA based hardware implementation of bat algorithmAppl Soft Comput20175837838710.1016/j.asoc.2017.04.015 – reference: Zhao Y, Zhao C, Liu Y. FPGA-Based Hardware Modeling on Pigeon-Inspired Optimization Algorithm. In: Asian Simulation Conference 2022 Dec 9 (pp. 407–423). Singapore: Springer Nature Singapore. – reference: Kennedy J. and Eberhart R. 1995. Particle swarm optimization (PSO). In: Proc. IEEE International Conference on Neural Networks, Perth, Australia, 1942–1948. – reference: Haval Sadeeq , Adnan Mohsin Abdulazeez , Hardware Implementation of Firefly Optimization Algorithm Using FPGAs, Advanced Science and Engineering (ICOASE)on 2018 International Conference, 2018, pp 30-35. – reference: AbualigahLThe arithmetic optimization algorithmComput Methods Appl Mech Eng20211376113609419929910.1016/j.cma.2020.113609 – reference: SadekBAMAnisSFpga implementation of parallel particle swarm optimization algorithm and compared with genetic algorithm”Int J Adv Comput Sci Appl2016785764 – reference: Jiang Q. et al. A parallel whale optimization algorithm and its implementation on FPGA. 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| SubjectTerms | Algorithms Central processing units Compilers Computer Science Computing time Convergence CPUs Design optimization Field programmable gate arrays Graphics processing units Heuristic methods Interpreters Optimization algorithms Parallel processing Physics Processor Architectures Programming Languages Reconfigurable hardware Simulation |
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