Performance analysis of multi-folded pipelined successive cancellation decoder architecture for polar code - D, Dinesh Kumar; R, Shantha Selvakumari (Sadhana (Bangalore), 2024)
Keywords: 5G mobile communication; Algorithms; Codes; Computer architecture; Critical path; Decoders; Decoding; Design; Engineering; Error correcting codes; Error correction; Error correction & detection; Fourier transforms; Hardware; Lookup tables; Network latency; Optimization techniques; Random access memory; Registers; Utilization; field programmable gate array (FPGA); Polar code; successive cancellation decoding; pipelining; vLSI architecture; folding