Performance analysis of multi-folded pipelined successive cancellation decoder architecture for polar code

• Published in: Sadhana (Bangalore) Vol. 49; no. 2; p. 144
• Main Authors: D, Dinesh Kumar, R, Shantha Selvakumari
• Format: Journal Article
• Language: English
• Published: New Delhi Springer India 13.04.2024; Springer Nature B.V
• Subjects: 5G mobile communication; Algorithms; Codes; Computer architecture; Critical path; Decoders; Decoding; Design; Engineering; Error correcting codes; Error correction; Error correction & detection; Fourier transforms; Hardware; Lookup tables; Network latency; Optimization techniques; Random access memory; Registers; Utilization; field programmable gate array (FPGA); Polar code; successive cancellation decoding; pipelining; vLSI architecture; folding
• ISSN: 0973-7677; 0256-2499; 0973-7677
• DOI: 10.1007/s12046-024-02503-1

Polar codes are the popular error-correcting codes and increased their attention after being adopted for the control channel in fifth-generation new radio (5G NR) standards. An efficient hardware architecture for polar code is often required with minimal encoding and decoding complexity. This work proposes a Multi-folded pipelined architecture and analyzes the performance in terms of latency, hardware utilization, and throughput. The designed architecture has two folded architectures interconnected in parallel to output 4-bits simultaneously. Folding transformations are used to reduce the number of idle processing elements (PEs) in every stage leading to the effective utilization of PE. Precomputation is effectively utilized in the PE to reduce the critical path delay, which improves the maximum operating frequency. A Loop-based shifting register (LSR) is employed to reduce the number of registers used. The analytical model for latency and utilization rate has been derived from the scheduling of the proposed architecture. The proposed design shows 63–71% higher hardware utilization than conventional semi-parallel design for code length N = 512 suitable for the physical downlink control channel (PDCCH) in 5G NR. The architecture is also implemented in Virtex-6, ZYNQ-Ultrascale+ MPSoC device for maximum supported code length of 5G NR, i.e., up to 2 10 , compared with the existing decoders. The proposed design also has the benefit of lesser look-up-table (LUT) consumption and zero random-access-memory (RAM) usage with some additional registers, making it suitable for resource-constraint applications.