Design and analysis of a dual mode CMOS field programmable analog array
This paper presents a novel field-programmable analog array （FPAA） architecture featuring a dual mode including discrete-time （DT） and continuous-time （CT） operation modes, along with a highly routable connection boxes （CBs） based interconnection lattice. The dual mode circuit for the FPAA is capabl...
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| Published in | Journal of semiconductors Vol. 35; no. 10; pp. 152 - 162 |
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| Main Author | |
| Format | Journal Article |
| Language | English |
| Published |
01.10.2014
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| Subjects | |
| Online Access | Get full text |
| ISSN | 1674-4926 |
| DOI | 10.1088/1674-4926/35/10/105011 |
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| Abstract | This paper presents a novel field-programmable analog array （FPAA） architecture featuring a dual mode including discrete-time （DT） and continuous-time （CT） operation modes, along with a highly routable connection boxes （CBs） based interconnection lattice. The dual mode circuit for the FPAA is capable of achieving targeted op- timal performance in different applications. The architecture utilizes routing switches in a CB not only for the signal interconnection purpose but also for control of the electrical charge transfer required in switched-capacitor circuits. This way, the performance of the circuit in either mode shall not be hampered with adding of programmability. The proposed FPAA is designed and implemented in a 0.18 μm standard CMOS process with a 3.3 V supply voltage. The result from post-layout simulation shows that a maximum bandwidth of 265 MHz through the interconnection network is achieved. The measured results from demonstrated examples show that the maximum signal bandwidth of up to 2 MHz in CT mode is obtained with the spurious free dynamic range of 54 dB, while the signal processing precision in DT mode reaches 96.4%. |
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| AbstractList | This paper presents a novel field-programmable analog array (FPAA) architecture featuring a dual mode including discrete-time (DT) and continuous-time (CT) operation modes, along with a highly routable connection boxes (CBs) based interconnection lattice. The dual mode circuit for the FPAA is capable of achieving targeted optimal performance in different applications. The architecture utilizes routing switches in a CB not only for the signal interconnection purpose but also for control of the electrical charge transfer required in switched-capacitor circuits. This way, the performance of the circuit in either mode shall not be hampered with adding of programmability. The proposed FPAA is designed and implemented in a 0.18 [mu]m standard CMOS process with a 3.3 V supply voltage. The result from post-layout simulation shows that a maximum bandwidth of 265 MHz through the interconnection network is achieved. The measured results from demonstrated examples show that the maximum signal bandwidth of up to 2 MHz in CT mode is obtained with the spurious free dynamic range of 54 dB, while the signal processing precision in DT mode reaches 96.4%. This paper presents a novel field-programmable analog array （FPAA） architecture featuring a dual mode including discrete-time （DT） and continuous-time （CT） operation modes, along with a highly routable connection boxes （CBs） based interconnection lattice. The dual mode circuit for the FPAA is capable of achieving targeted op- timal performance in different applications. The architecture utilizes routing switches in a CB not only for the signal interconnection purpose but also for control of the electrical charge transfer required in switched-capacitor circuits. This way, the performance of the circuit in either mode shall not be hampered with adding of programmability. The proposed FPAA is designed and implemented in a 0.18 μm standard CMOS process with a 3.3 V supply voltage. The result from post-layout simulation shows that a maximum bandwidth of 265 MHz through the interconnection network is achieved. The measured results from demonstrated examples show that the maximum signal bandwidth of up to 2 MHz in CT mode is obtained with the spurious free dynamic range of 54 dB, while the signal processing precision in DT mode reaches 96.4%. |
| Author | 程小燕 杨海钢 尹韬 吴其松 张洪锋 刘飞 |
| AuthorAffiliation | Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China University of Chinese Academy of Sciences, Beijing 100049, China |
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| Cites_doi | 10.1109/4.551908 10.1109/TVLSI.2012.2211049 10.1007/s10470-010-9566-5 10.1109/JSSC.2008.2005697 10.1109/92.920839 10.1109/JSSC.2003.814430 10.1109/JSSC.2010.2056832 10.1109/4.340424 10.1109/4.104162 |
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| DocumentTitleAlternate | Design and analysis of a dual mode CMOS field programmable analog array |
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| Notes | field-programmable gate array; field-programmable analog array; configurable analog block; rail-to- rail; biquadratic filters This paper presents a novel field-programmable analog array （FPAA） architecture featuring a dual mode including discrete-time （DT） and continuous-time （CT） operation modes, along with a highly routable connection boxes （CBs） based interconnection lattice. The dual mode circuit for the FPAA is capable of achieving targeted op- timal performance in different applications. The architecture utilizes routing switches in a CB not only for the signal interconnection purpose but also for control of the electrical charge transfer required in switched-capacitor circuits. This way, the performance of the circuit in either mode shall not be hampered with adding of programmability. The proposed FPAA is designed and implemented in a 0.18 μm standard CMOS process with a 3.3 V supply voltage. The result from post-layout simulation shows that a maximum bandwidth of 265 MHz through the interconnection network is achieved. The measured results from demonstrated examples show that the maximum signal bandwidth of up to 2 MHz in CT mode is obtained with the spurious free dynamic range of 54 dB, while the signal processing precision in DT mode reaches 96.4%. 11-5781/TN Cheng Xiaoyan, Yang Haigang, Yin Tao, Wu Qisong,Zhang Hongfeng,Liu Fei（1 Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China 2University of Chinese Academy of Sciences, Beijing 100049, China） ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23 |
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| PublicationTitle | Journal of semiconductors |
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| References | 12 13 14 15 16 Luo J (6) 2005 Hasler P E (8) 2007 Mohan P V A (11) 1995 Cheng X Y (7) 2013 Sivilotti M A (1) 1988 2 3 4 5 Brown T W (9) 2006 Gregorian R (10) 1986 |
| References_xml | – ident: 12 doi: 10.1109/4.551908 – ident: 16 doi: 10.1109/TVLSI.2012.2211049 – year: 1995 ident: 11 publication-title: Switched capacitor filters: theory, analysis and design – year: 2005 ident: 6 – ident: 15 doi: 10.1007/s10470-010-9566-5 – ident: 2 doi: 10.1109/JSSC.2008.2005697 – ident: 3 doi: 10.1109/92.920839 – start-page: 177 year: 2007 ident: 8 – year: 1986 ident: 10 publication-title: Analog MOS integrated circuits for signal processing – start-page: 2 year: 2013 ident: 7 – ident: 14 doi: 10.1109/JSSC.2003.814430 – year: 2006 ident: 9 publication-title: Prediction and characterization of frequency dependent MOS switch linearity and the design implications – ident: 5 doi: 10.1109/JSSC.2010.2056832 – ident: 13 doi: 10.1109/4.340424 – ident: 4 doi: 10.1109/4.104162 – start-page: 237 year: 1988 ident: 1 |
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| Snippet | This paper presents a novel field-programmable analog array （FPAA） architecture featuring a dual mode including discrete-time （DT） and continuous-time... This paper presents a novel field-programmable analog array (FPAA) architecture featuring a dual mode including discrete-time (DT) and continuous-time (CT)... |
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| SubjectTerms | Architecture Arrays Circuits CMOS CMOS工艺 FPAA Interconnection Lattice vibration Semiconductors Signal processing 互连网络 信号带宽 双模式 现场可编程模拟阵列 设计 路由交换机 |
| Title | Design and analysis of a dual mode CMOS field programmable analog array |
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