Analytical model for high-voltage SOI device with composite-k dielectric buried layer - 范杰 张波 罗小蓉 汪志刚 李肇基 (Journal of semiconductors, 2013)
An analytical model for a novel high voltage silicon-on-insulator device with composite-k （relative per mittivity） dielectric buried layer （CK SOl） is proposed. In this structure, the composite-k buried layer is composed by alternating Si3N4 and low-k （k = 2.65） dielectric in the lateral direction. Due to the composite-k buried layer, the breakdown voltage （BV） is improved both by the vertical and lateral direction. Taking the modulation effect of accumulated interface holes into account, an analytical model is developed. In the blocking state, the proposed model revealed the mechanism of hole accumulation above the Si3N4 buried layer and investigated the modulation effect of accumulated holes on the two-dimensional （2-D） potential and electric field distributions. This analytical model is verified by the simulation results. Compared with the low-k dielectric buried layer SO1 （LK SOl）, simu lation results show that the BV for CK SOl is enhanced by 21% and the specific on-resistance is reduced by 32%, respectively.