Some Comments Concerning Design of Pipeline Arithmetic Arrays

• Published in: IEEE transactions on computers Vol. C-25; no. 11; pp. 1132 - 1134
• Main Author: Majithia
• Format: Journal Article
• Language: English
• Published: IEEE 01.11.1976
• Subjects: Cellular arrays; figure of merit; parallel processes; pipelining
• ISSN: 0018-9340
• DOI: 10.1109/TC.1976.1674565

Cellular arrays for arithmetic operations usually consist of identical cells connected in an iterative or near iterative pattern. By introducing latch circuits between the rows of the array, the entire unit can be pipelined. The effect of this modification is to increase the throughput on a continuous processing basis. In most of such designs, however, the amount of hardware required for a maximally or fully pipelined array is prohibitively large. Pipeline arrays with reduced amount of intermediate latch circuits imply partially pipelined designs which of course also have a lower throughput. However, several such pipeline arrays can be operated in parallel to achieve some specified total throughput. In this correspondence this aspect is analyzed and illustrated by the design of 48-bit parallel adders.