Efficient topology reconfiguration for NoC-based multiprocessors: A greedy-memetic algorithm

In multi-core processor systems, the Network-on-Chip (NoC) serves as a vital communication infrastructure. To ensure chip reliability during potential failures, this paper proposes a two-level topology reconfiguration algorithm with core-level redundancy technology. Initially, a heuristic topology r...

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Published inJournal of parallel and distributed computing Vol. 190; p. 104904
Main Authors Qian, Junyan, Zhang, Chuanfang, Wu, Zheng, Ding, Hao, Li, Long
Format Journal Article
LanguageEnglish
Published Elsevier Inc 01.08.2024
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Online AccessGet full text
ISSN0743-7315
1096-0848
DOI10.1016/j.jpdc.2024.104904

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Abstract In multi-core processor systems, the Network-on-Chip (NoC) serves as a vital communication infrastructure. To ensure chip reliability during potential failures, this paper proposes a two-level topology reconfiguration algorithm with core-level redundancy technology. Initially, a heuristic topology reconfiguration method utilizing a greedy strategy is proposed to perform local replacement of faulty processing elements (PEs) and generate an initial logical topology with shorter interconnection paths between PEs. Then, an intelligent optimization method based on memetic algorithm is introduced to optimize the generated initial topology for better communication performance. The experimental results demonstrate that compared to the current state-of-the-art algorithm, the proposed algorithm achieves an average improvement of 13.92% and 30.83% on various size topologies in terms of distance factor (DF) and congestion factor (CF), which represent communication delay and traffic balance respectively. The proposed algorithm significantly enhances the communication performance of the target topology, mitigating communication latency and potential congestion problems. •The candidate set aids greedy selection for optimal fault-free PE replacements.•Local greedy strategy reduces communication delay, eases congestion issues.•Memetic algorithm further optimizes the target topology in the reconfiguration.•The proposed algorithms show strong stability, adaptability in large-scale arrays.
AbstractList In multi-core processor systems, the Network-on-Chip (NoC) serves as a vital communication infrastructure. To ensure chip reliability during potential failures, this paper proposes a two-level topology reconfiguration algorithm with core-level redundancy technology. Initially, a heuristic topology reconfiguration method utilizing a greedy strategy is proposed to perform local replacement of faulty processing elements (PEs) and generate an initial logical topology with shorter interconnection paths between PEs. Then, an intelligent optimization method based on memetic algorithm is introduced to optimize the generated initial topology for better communication performance. The experimental results demonstrate that compared to the current state-of-the-art algorithm, the proposed algorithm achieves an average improvement of 13.92% and 30.83% on various size topologies in terms of distance factor (DF) and congestion factor (CF), which represent communication delay and traffic balance respectively. The proposed algorithm significantly enhances the communication performance of the target topology, mitigating communication latency and potential congestion problems. •The candidate set aids greedy selection for optimal fault-free PE replacements.•Local greedy strategy reduces communication delay, eases congestion issues.•Memetic algorithm further optimizes the target topology in the reconfiguration.•The proposed algorithms show strong stability, adaptability in large-scale arrays.
ArticleNumber 104904
Author Qian, Junyan
Ding, Hao
Zhang, Chuanfang
Li, Long
Wu, Zheng
Author_xml – sequence: 1
  givenname: Junyan
  orcidid: 0000-0002-1325-6975
  surname: Qian
  fullname: Qian, Junyan
  email: qjy2000@gmail.com
  organization: Key Laboratory of Education Blockchain and Intelligent Technology, Ministry of Education, Guangxi Normal University, Guilin, 541004, China
– sequence: 2
  givenname: Chuanfang
  surname: Zhang
  fullname: Zhang, Chuanfang
  email: gromezhang@gmail.com
  organization: Key Laboratory of Education Blockchain and Intelligent Technology, Ministry of Education, Guangxi Normal University, Guilin, 541004, China
– sequence: 3
  givenname: Zheng
  orcidid: 0009-0003-5523-6029
  surname: Wu
  fullname: Wu, Zheng
  email: wuzhengtotoro@outlook.com
  organization: Key Laboratory of Education Blockchain and Intelligent Technology, Ministry of Education, Guangxi Normal University, Guilin, 541004, China
– sequence: 4
  givenname: Hao
  orcidid: 0000-0001-5325-9997
  surname: Ding
  fullname: Ding, Hao
  email: dhguet@gmail.com
  organization: Key Laboratory of Education Blockchain and Intelligent Technology, Ministry of Education, Guangxi Normal University, Guilin, 541004, China
– sequence: 5
  givenname: Long
  orcidid: 0000-0002-7693-9722
  surname: Li
  fullname: Li, Long
  email: lilong@guet.edu.cn
  organization: Guangxi Key Laboratory of Trusted Software, Guilin University of Electronic Technology, Guilin 541004, China
BookMark eNp90FtLwzAUwPEgCm7TL-BTvkBnrm0qvowxLzD0Rd-EkOVSU9qmJJmwb2_LfPbpwIH_4fBbgsshDBaAO4zWGOHyvl23o9FrggibFqxG7AIsMKrLAgkmLsECVYwWFcX8GixTahHCmFdiAb52znnt7ZBhDmPoQnOC0eowON8co8o-DNCFCN_CtjioZA3sj132YwzaphRieoAb2ERrzanobW-z11B1TYg-f_c34MqpLtnbv7kCn0-7j-1LsX9_ft1u9oUmHOdCkZpjRhXFpXBlqStaU3QwpBbswB2pFHUCc-QoxVgrXhFUCY4RpczUlJuSrgA539UxpBStk2P0vYoniZGcfWQrZx85-8izzxQ9niM7ffbjbZRpdtDW-AkgSxP8f_kvbX1wQw
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ContentType Journal Article
Copyright 2024 Elsevier Inc.
Copyright_xml – notice: 2024 Elsevier Inc.
DBID AAYXX
CITATION
DOI 10.1016/j.jpdc.2024.104904
DatabaseName CrossRef
DatabaseTitle CrossRef
DatabaseTitleList
DeliveryMethod fulltext_linktorsrc
Discipline Computer Science
EISSN 1096-0848
ExternalDocumentID 10_1016_j_jpdc_2024_104904
S0743731524000686
GroupedDBID --K
--M
-~X
.~1
0R~
1B1
1~.
1~5
29L
4.4
457
4G.
5GY
5VS
7-5
71M
8P~
9JN
AACTN
AAEDT
AAEDW
AAIAV
AAIKJ
AAKOC
AALRI
AAOAW
AAQFI
AAQXK
AAXUO
AAYFN
ABBOA
ABEFU
ABFNM
ABFSI
ABJNI
ABMAC
ABTAH
ABXDB
ACDAQ
ACGFS
ACNNM
ACRLP
ACZNC
ADBBV
ADEZE
ADFGL
ADHUB
ADJOM
ADMUD
ADTZH
AEBSH
AECPX
AEKER
AENEX
AFKWA
AFTJW
AGHFR
AGUBO
AGYEJ
AHHHB
AHJVU
AHZHX
AIALX
AIEXJ
AIKHN
AITUG
AJOXV
AKRWK
ALMA_UNASSIGNED_HOLDINGS
AMFUW
AMRAJ
AOUOD
ASPBG
AVWKF
AXJTR
AZFZN
BJAXD
BKOJK
BLXMC
CAG
COF
CS3
DM4
DU5
E.L
EBS
EFBJH
EJD
EO8
EO9
EP2
EP3
F5P
FDB
FEDTE
FGOYB
FIRID
FNPLU
FYGXN
G-2
G-Q
G8K
GBLVA
GBOLZ
HLZ
HVGLF
HZ~
H~9
IHE
J1W
JJJVA
K-O
KOM
LG5
LG9
LY7
M41
MO0
N9A
O-L
O9-
OAUVE
OZT
P-8
P-9
P2P
PC.
Q38
R2-
RIG
ROL
RPZ
SBC
SDF
SDG
SDP
SES
SET
SEW
SPC
SPCBC
SST
SSV
SSZ
T5K
TN5
TWZ
WUQ
XJT
XOL
XPP
ZMT
ZU3
ZY4
~G-
~G0
AATTM
AAXKI
AAYWO
AAYXX
ABDPE
ABWVN
ACLOT
ACRPL
ACVFH
ADCNI
ADNMO
ADVLN
AEIPS
AEUPX
AFJKZ
AFPUW
AGQPQ
AIGII
AIIUN
AKBMS
AKYEP
ANKPU
APXCP
CITATION
EFKBS
EFLBG
~HD
ID FETCH-LOGICAL-c251t-a295143a3168f66c73930bd2984b5f27a3f8150f3311ca572078510334d935d63
IEDL.DBID .~1
ISSN 0743-7315
IngestDate Wed Oct 01 04:01:42 EDT 2025
Sat May 11 15:33:15 EDT 2024
IsPeerReviewed true
IsScholarly true
Keywords Topology reconfiguration
Core-level redundancy
Fault-tolerant
Multiprocessor array
Algorithm
Network on chip
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-c251t-a295143a3168f66c73930bd2984b5f27a3f8150f3311ca572078510334d935d63
ORCID 0000-0002-7693-9722
0009-0003-5523-6029
0000-0001-5325-9997
0000-0002-1325-6975
ParticipantIDs crossref_primary_10_1016_j_jpdc_2024_104904
elsevier_sciencedirect_doi_10_1016_j_jpdc_2024_104904
ProviderPackageCode CITATION
AAYXX
PublicationCentury 2000
PublicationDate August 2024
2024-08-00
PublicationDateYYYYMMDD 2024-08-01
PublicationDate_xml – month: 08
  year: 2024
  text: August 2024
PublicationDecade 2020
PublicationTitle Journal of parallel and distributed computing
PublicationYear 2024
Publisher Elsevier Inc
Publisher_xml – name: Elsevier Inc
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SSID ssj0011578
Score 2.4043293
Snippet In multi-core processor systems, the Network-on-Chip (NoC) serves as a vital communication infrastructure. To ensure chip reliability during potential...
SourceID crossref
elsevier
SourceType Index Database
Publisher
StartPage 104904
SubjectTerms Algorithm
Core-level redundancy
Fault-tolerant
Multiprocessor array
Network on chip
Topology reconfiguration
Title Efficient topology reconfiguration for NoC-based multiprocessors: A greedy-memetic algorithm
URI https://dx.doi.org/10.1016/j.jpdc.2024.104904
Volume 190
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
journalDatabaseRights – providerCode: PRVESC
  databaseName: Baden-Württemberg Complete Freedom Collection (Elsevier)
  customDbUrl:
  eissn: 1096-0848
  dateEnd: 99991231
  omitProxy: true
  ssIdentifier: ssj0011578
  issn: 0743-7315
  databaseCode: GBLVA
  dateStart: 20110101
  isFulltext: true
  titleUrlDefault: https://www.sciencedirect.com
  providerName: Elsevier
– providerCode: PRVESC
  databaseName: Elsevier Science Direct Journals
  customDbUrl:
  eissn: 1096-0848
  dateEnd: 99991231
  omitProxy: true
  ssIdentifier: ssj0011578
  issn: 0743-7315
  databaseCode: AIKHN
  dateStart: 19950101
  isFulltext: true
  titleUrlDefault: https://www.sciencedirect.com
  providerName: Elsevier
– providerCode: PRVESC
  databaseName: Elsevier ScienceDirect
  customDbUrl:
  eissn: 1096-0848
  dateEnd: 99991231
  omitProxy: true
  ssIdentifier: ssj0011578
  issn: 0743-7315
  databaseCode: .~1
  dateStart: 19950101
  isFulltext: true
  titleUrlDefault: https://www.sciencedirect.com
  providerName: Elsevier
– providerCode: PRVESC
  databaseName: Elsevier SD Complete Freedom Collection [SCCMFC]
  customDbUrl:
  eissn: 1096-0848
  dateEnd: 99991231
  omitProxy: true
  ssIdentifier: ssj0011578
  issn: 0743-7315
  databaseCode: ACRLP
  dateStart: 19950101
  isFulltext: true
  titleUrlDefault: https://www.sciencedirect.com
  providerName: Elsevier
– providerCode: PRVLSH
  databaseName: Elsevier Journals
  customDbUrl:
  mediaType: online
  eissn: 1096-0848
  dateEnd: 99991231
  omitProxy: true
  ssIdentifier: ssj0011578
  issn: 0743-7315
  databaseCode: AKRWK
  dateStart: 19840801
  isFulltext: true
  providerName: Library Specific Holdings
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwnV1NS8NAEB1KvXjxW2zVsgdvEpsm2Xx4K6WlKvSihR6EkGR3a4ptSk0PXvztzmQ3oggePCZkIcwmM2-S994AXAUk1uxJZZGIk75WOZQHA8uJbIFwREns5ohtMfHHU-9-xmcNGNRaGKJVmtyvc3qVrc2Zrolmd53n3UcqfoGL9cezK6EDKdi9gKYY3Hx80TzISyasrTjpaiOc0RyvxVqQjaHj0a_OyAxr-1WcvhWc0QHsGaTI-vpmDqEhV0ewX09hYOalPIbnYeUCgcWDlXriwTur2lyVz7d6fxkiUzYpBhbVLME0iVArBIrN2y3rM-y6Md1aS7kkUSNLXufFJi9flicwHQ2fBmPLzEywMkQqpZU4EUGghOZRKd_PyPDOToUThV7KlRMkrgoRAyrX7fWyhAcOQgQy1XM9Eblc-O4pNFfFSp4BC1MuqB3zEeF5uJOJQjQhbJ7JQCVS-C24roMVr7U1RlxzxhYxhTam0MY6tC3gdTzjHxscY-7-Y137n-vOYZeONFfvAprlZisvET-Uaad6QDqw0797GE8-AcVawr0
linkProvider Elsevier
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwnV09T8MwED2VMsDCN6J8emBDoakT54OtqooKlC60UgckK4njkoo2VUkHFn47vthBICQG1iSWonNy9y557x3ApY9izVYqLRRx4tcqinnQt2hoCwVHZKq6OWRbDLzeyL0fs3ENOpUWBmmVJvfrnF5ma3OkaaLZXGRZ8wmLn--o-uPapdBhDdZdRn3swK4_vngeaCYTVF6ceLlRzmiS13Qh0MeQuvivMzTT2n5Vp28V53YHtgxUJG19N7tQS-d7sF2NYSDmrdyH525pA6GqByn0yIN3Uva5Mpus9AYTBU3JIO9YWLQE0SxCLRHIl283pE1U263yrTVLZ6hqJNHrJF9mxcvsAEa33WGnZ5mhCVaioEphRTREDBThQCrpeQk63tmxoGHgxkxSP3JkoECgdJxWK4mYTxVGQFc9xxWhw4TnHEJ9ns_TIyBBzAT2Y56CeK7aykgqOCFslqS-jFLhNeCqChZfaG8MXpHGphxDyzG0XIe2AayKJ_-xw1wl7z_WHf9z3QVs9IaPfd6_GzycwCae0cS9U6gXy1V6psBEEZ-XD8snhoHEUg
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Efficient+topology+reconfiguration+for+NoC-based+multiprocessors%3A+A+greedy-memetic+algorithm&rft.jtitle=Journal+of+parallel+and+distributed+computing&rft.au=Qian%2C+Junyan&rft.au=Zhang%2C+Chuanfang&rft.au=Wu%2C+Zheng&rft.au=Ding%2C+Hao&rft.date=2024-08-01&rft.issn=0743-7315&rft.volume=190&rft.spage=104904&rft_id=info:doi/10.1016%2Fj.jpdc.2024.104904&rft.externalDBID=n%2Fa&rft.externalDocID=10_1016_j_jpdc_2024_104904
thumbnail_l http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=0743-7315&client=summon
thumbnail_m http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=0743-7315&client=summon
thumbnail_s http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=0743-7315&client=summon