Efficient topology reconfiguration for NoC-based multiprocessors: A greedy-memetic algorithm
In multi-core processor systems, the Network-on-Chip (NoC) serves as a vital communication infrastructure. To ensure chip reliability during potential failures, this paper proposes a two-level topology reconfiguration algorithm with core-level redundancy technology. Initially, a heuristic topology r...
        Saved in:
      
    
          | Published in | Journal of parallel and distributed computing Vol. 190; p. 104904 | 
|---|---|
| Main Authors | , , , , | 
| Format | Journal Article | 
| Language | English | 
| Published | 
            Elsevier Inc
    
        01.08.2024
     | 
| Subjects | |
| Online Access | Get full text | 
| ISSN | 0743-7315 1096-0848  | 
| DOI | 10.1016/j.jpdc.2024.104904 | 
Cover
| Abstract | In multi-core processor systems, the Network-on-Chip (NoC) serves as a vital communication infrastructure. To ensure chip reliability during potential failures, this paper proposes a two-level topology reconfiguration algorithm with core-level redundancy technology. Initially, a heuristic topology reconfiguration method utilizing a greedy strategy is proposed to perform local replacement of faulty processing elements (PEs) and generate an initial logical topology with shorter interconnection paths between PEs. Then, an intelligent optimization method based on memetic algorithm is introduced to optimize the generated initial topology for better communication performance. The experimental results demonstrate that compared to the current state-of-the-art algorithm, the proposed algorithm achieves an average improvement of 13.92% and 30.83% on various size topologies in terms of distance factor (DF) and congestion factor (CF), which represent communication delay and traffic balance respectively. The proposed algorithm significantly enhances the communication performance of the target topology, mitigating communication latency and potential congestion problems.
•The candidate set aids greedy selection for optimal fault-free PE replacements.•Local greedy strategy reduces communication delay, eases congestion issues.•Memetic algorithm further optimizes the target topology in the reconfiguration.•The proposed algorithms show strong stability, adaptability in large-scale arrays. | 
    
|---|---|
| AbstractList | In multi-core processor systems, the Network-on-Chip (NoC) serves as a vital communication infrastructure. To ensure chip reliability during potential failures, this paper proposes a two-level topology reconfiguration algorithm with core-level redundancy technology. Initially, a heuristic topology reconfiguration method utilizing a greedy strategy is proposed to perform local replacement of faulty processing elements (PEs) and generate an initial logical topology with shorter interconnection paths between PEs. Then, an intelligent optimization method based on memetic algorithm is introduced to optimize the generated initial topology for better communication performance. The experimental results demonstrate that compared to the current state-of-the-art algorithm, the proposed algorithm achieves an average improvement of 13.92% and 30.83% on various size topologies in terms of distance factor (DF) and congestion factor (CF), which represent communication delay and traffic balance respectively. The proposed algorithm significantly enhances the communication performance of the target topology, mitigating communication latency and potential congestion problems.
•The candidate set aids greedy selection for optimal fault-free PE replacements.•Local greedy strategy reduces communication delay, eases congestion issues.•Memetic algorithm further optimizes the target topology in the reconfiguration.•The proposed algorithms show strong stability, adaptability in large-scale arrays. | 
    
| ArticleNumber | 104904 | 
    
| Author | Qian, Junyan Ding, Hao Zhang, Chuanfang Li, Long Wu, Zheng  | 
    
| Author_xml | – sequence: 1 givenname: Junyan orcidid: 0000-0002-1325-6975 surname: Qian fullname: Qian, Junyan email: qjy2000@gmail.com organization: Key Laboratory of Education Blockchain and Intelligent Technology, Ministry of Education, Guangxi Normal University, Guilin, 541004, China – sequence: 2 givenname: Chuanfang surname: Zhang fullname: Zhang, Chuanfang email: gromezhang@gmail.com organization: Key Laboratory of Education Blockchain and Intelligent Technology, Ministry of Education, Guangxi Normal University, Guilin, 541004, China – sequence: 3 givenname: Zheng orcidid: 0009-0003-5523-6029 surname: Wu fullname: Wu, Zheng email: wuzhengtotoro@outlook.com organization: Key Laboratory of Education Blockchain and Intelligent Technology, Ministry of Education, Guangxi Normal University, Guilin, 541004, China – sequence: 4 givenname: Hao orcidid: 0000-0001-5325-9997 surname: Ding fullname: Ding, Hao email: dhguet@gmail.com organization: Key Laboratory of Education Blockchain and Intelligent Technology, Ministry of Education, Guangxi Normal University, Guilin, 541004, China – sequence: 5 givenname: Long orcidid: 0000-0002-7693-9722 surname: Li fullname: Li, Long email: lilong@guet.edu.cn organization: Guangxi Key Laboratory of Trusted Software, Guilin University of Electronic Technology, Guilin 541004, China  | 
    
| BookMark | eNp90FtLwzAUwPEgCm7TL-BTvkBnrm0qvowxLzD0Rd-EkOVSU9qmJJmwb2_LfPbpwIH_4fBbgsshDBaAO4zWGOHyvl23o9FrggibFqxG7AIsMKrLAgkmLsECVYwWFcX8GixTahHCmFdiAb52znnt7ZBhDmPoQnOC0eowON8co8o-DNCFCN_CtjioZA3sj132YwzaphRieoAb2ERrzanobW-z11B1TYg-f_c34MqpLtnbv7kCn0-7j-1LsX9_ft1u9oUmHOdCkZpjRhXFpXBlqStaU3QwpBbswB2pFHUCc-QoxVgrXhFUCY4RpczUlJuSrgA539UxpBStk2P0vYoniZGcfWQrZx85-8izzxQ9niM7ffbjbZRpdtDW-AkgSxP8f_kvbX1wQw | 
    
| Cites_doi | 10.1109/TCAD.2011.2138430 10.1007/s10589-005-4562-x 10.1016/j.sysarc.2013.03.010 10.1016/j.jpdc.2014.06.009 10.1109/TC.2015.2389846 10.1016/j.jpdc.2021.08.005 10.1109/ACCESS.2021.3066537 10.1049/iet-cdt.2013.0032 10.1109/TCAD.2019.2891984 10.1109/TC.2021.3071507 10.1016/S1007-0214(07)70104-9 10.1016/j.swevo.2011.11.003 10.1016/j.epsr.2010.01.001 10.1155/2007/95348 10.1142/S0218126619501111 10.1109/TVLSI.2008.2002108 10.1109/ACCESS.2021.3100540  | 
    
| ContentType | Journal Article | 
    
| Copyright | 2024 Elsevier Inc. | 
    
| Copyright_xml | – notice: 2024 Elsevier Inc. | 
    
| DBID | AAYXX CITATION  | 
    
| DOI | 10.1016/j.jpdc.2024.104904 | 
    
| DatabaseName | CrossRef | 
    
| DatabaseTitle | CrossRef | 
    
| DatabaseTitleList | |
| DeliveryMethod | fulltext_linktorsrc | 
    
| Discipline | Computer Science | 
    
| EISSN | 1096-0848 | 
    
| ExternalDocumentID | 10_1016_j_jpdc_2024_104904 S0743731524000686  | 
    
| GroupedDBID | --K --M -~X .~1 0R~ 1B1 1~. 1~5 29L 4.4 457 4G. 5GY 5VS 7-5 71M 8P~ 9JN AACTN AAEDT AAEDW AAIAV AAIKJ AAKOC AALRI AAOAW AAQFI AAQXK AAXUO AAYFN ABBOA ABEFU ABFNM ABFSI ABJNI ABMAC ABTAH ABXDB ACDAQ ACGFS ACNNM ACRLP ACZNC ADBBV ADEZE ADFGL ADHUB ADJOM ADMUD ADTZH AEBSH AECPX AEKER AENEX AFKWA AFTJW AGHFR AGUBO AGYEJ AHHHB AHJVU AHZHX AIALX AIEXJ AIKHN AITUG AJOXV AKRWK ALMA_UNASSIGNED_HOLDINGS AMFUW AMRAJ AOUOD ASPBG AVWKF AXJTR AZFZN BJAXD BKOJK BLXMC CAG COF CS3 DM4 DU5 E.L EBS EFBJH EJD EO8 EO9 EP2 EP3 F5P FDB FEDTE FGOYB FIRID FNPLU FYGXN G-2 G-Q G8K GBLVA GBOLZ HLZ HVGLF HZ~ H~9 IHE J1W JJJVA K-O KOM LG5 LG9 LY7 M41 MO0 N9A O-L O9- OAUVE OZT P-8 P-9 P2P PC. Q38 R2- RIG ROL RPZ SBC SDF SDG SDP SES SET SEW SPC SPCBC SST SSV SSZ T5K TN5 TWZ WUQ XJT XOL XPP ZMT ZU3 ZY4 ~G- ~G0 AATTM AAXKI AAYWO AAYXX ABDPE ABWVN ACLOT ACRPL ACVFH ADCNI ADNMO ADVLN AEIPS AEUPX AFJKZ AFPUW AGQPQ AIGII AIIUN AKBMS AKYEP ANKPU APXCP CITATION EFKBS EFLBG ~HD  | 
    
| ID | FETCH-LOGICAL-c251t-a295143a3168f66c73930bd2984b5f27a3f8150f3311ca572078510334d935d63 | 
    
| IEDL.DBID | .~1 | 
    
| ISSN | 0743-7315 | 
    
| IngestDate | Wed Oct 01 04:01:42 EDT 2025 Sat May 11 15:33:15 EDT 2024  | 
    
| IsPeerReviewed | true | 
    
| IsScholarly | true | 
    
| Keywords | Topology reconfiguration Core-level redundancy Fault-tolerant Multiprocessor array Algorithm Network on chip  | 
    
| Language | English | 
    
| LinkModel | DirectLink | 
    
| MergedId | FETCHMERGED-LOGICAL-c251t-a295143a3168f66c73930bd2984b5f27a3f8150f3311ca572078510334d935d63 | 
    
| ORCID | 0000-0002-7693-9722 0009-0003-5523-6029 0000-0001-5325-9997 0000-0002-1325-6975  | 
    
| ParticipantIDs | crossref_primary_10_1016_j_jpdc_2024_104904 elsevier_sciencedirect_doi_10_1016_j_jpdc_2024_104904  | 
    
| ProviderPackageCode | CITATION AAYXX  | 
    
| PublicationCentury | 2000 | 
    
| PublicationDate | August 2024 2024-08-00  | 
    
| PublicationDateYYYYMMDD | 2024-08-01 | 
    
| PublicationDate_xml | – month: 08 year: 2024 text: August 2024  | 
    
| PublicationDecade | 2020 | 
    
| PublicationTitle | Journal of parallel and distributed computing | 
    
| PublicationYear | 2024 | 
    
| Publisher | Elsevier Inc | 
    
| Publisher_xml | – name: Elsevier Inc | 
    
| References | Li, Yan, Liu (br0150) 2023 Bhanu, Govindan, Kattamuri (br0270) 2021; 9 Chou, Marculescu (br0380) 2011 Guan, Cai, Wang (br0070) 2020 Murali, Atienza, Benini (br0340) 2006 Sarihi, Patooghy, Khalid (br0030) 2021; 9 Jiang, Wu, Ha (br0300) 2015; 64 Wang, Wu, Jiang (br0240) 2013 Beechu, Harishchandra, Balachandra (br0400) 2017; 16 Xiao, Nazarian, Bogdan (br0120) 2021; 70 Jiang, Wu, Sun (br0320) 2014; 74 Schuchman, Vijaykumar (br0170) 2005 Bogdan, Dumitras, Marculescu (br0090) 2007 Bogdan, Kas, Marculescu (br0440) 2010 Dubrova (br0140) 2008 Neri, Cotta (br0460) 2012; 2 Ren, Liu, Yin (br0210) 2013; 59 Harris, Berretta, Inostroza-Ponta (br0450) 2015 Reddy, Vasantha, Kumar (br0260) 2015 Reddy, Vasantha, YB (br0360) 2016; 5 Weaver, Austin (br0160) 2001 Zhang, Greiner, Taktak (br0180) 2008 Zhang, Han, Xu (br0220) 2009; 17 Qian, Bogdan, Wei (br0100) 2012 Reddy, Vasantha, Kumar (br0250) 2016 Zhang, Han, Li (br0410) 2007; 12 Xue, Bogdan (br0110) 2015 Zhang, Han, Xu (br0230) 2008 Ebrahimi, Daneshtalab, Plosila (br0200) 2013 Bogdan, Marculescu (br0080) 2011; 30 Khalili, Zarandi (br0390) 2012 Misevicius (br0480) 2005; 30 Liu, Ren, Deng (br0350) 2015 Chang, Chiu, Lin (br0190) 2011 Mercier, Killian, Kritikakou (br0050) 2022; 10 Venkatesha, Parthasarathi (br0280) 2022 Xue, Bogdan (br0130) 2016 Siddagangappa, Nayana (br0040) 2022 Wu, Wu, Jiang (br0420) 2019; 28 Abdelaziz, Mohamed, Mekhamer (br0470) 2010; 80 Li, Zeng, Jone (br0430) 2006 Qian, Ding, Xiao (br0290) 2020; 39 Khalili, Zarandi (br0370) 2013; 7 Peng, Wen, Bhadra (br0060) 2009 Ding, Qian, Zhao (br0310) 2021; 158 Janac, Charles (br0010) 2021 Grecu, Pande, Ivanov (br0020) 2004 Wang, Wu, Wen (br0330) 2006 Janac (10.1016/j.jpdc.2024.104904_br0010) 2021 Li (10.1016/j.jpdc.2024.104904_br0430) 2006 Wang (10.1016/j.jpdc.2024.104904_br0240) 2013 Bogdan (10.1016/j.jpdc.2024.104904_br0440) 2010 Jiang (10.1016/j.jpdc.2024.104904_br0300) 2015; 64 Grecu (10.1016/j.jpdc.2024.104904_br0020) 2004 Liu (10.1016/j.jpdc.2024.104904_br0350) 2015 Ren (10.1016/j.jpdc.2024.104904_br0210) 2013; 59 Ding (10.1016/j.jpdc.2024.104904_br0310) 2021; 158 Misevicius (10.1016/j.jpdc.2024.104904_br0480) 2005; 30 Harris (10.1016/j.jpdc.2024.104904_br0450) 2015 Xiao (10.1016/j.jpdc.2024.104904_br0120) 2021; 70 Mercier (10.1016/j.jpdc.2024.104904_br0050) 2022; 10 Bhanu (10.1016/j.jpdc.2024.104904_br0270) 2021; 9 Neri (10.1016/j.jpdc.2024.104904_br0460) 2012; 2 Ebrahimi (10.1016/j.jpdc.2024.104904_br0200) 2013 Jiang (10.1016/j.jpdc.2024.104904_br0320) 2014; 74 Qian (10.1016/j.jpdc.2024.104904_br0290) 2020; 39 Sarihi (10.1016/j.jpdc.2024.104904_br0030) 2021; 9 Venkatesha (10.1016/j.jpdc.2024.104904_br0280) Reddy (10.1016/j.jpdc.2024.104904_br0360) 2016; 5 Zhang (10.1016/j.jpdc.2024.104904_br0220) 2009; 17 Qian (10.1016/j.jpdc.2024.104904_br0100) 2012 Dubrova (10.1016/j.jpdc.2024.104904_br0140) 2008 Li (10.1016/j.jpdc.2024.104904_br0150) 2023 Wu (10.1016/j.jpdc.2024.104904_br0420) 2019; 28 Zhang (10.1016/j.jpdc.2024.104904_br0180) 2008 Wang (10.1016/j.jpdc.2024.104904_br0330) 2006 Beechu (10.1016/j.jpdc.2024.104904_br0400) 2017; 16 Guan (10.1016/j.jpdc.2024.104904_br0070) 2020 Zhang (10.1016/j.jpdc.2024.104904_br0230) 2008 Schuchman (10.1016/j.jpdc.2024.104904_br0170) 2005 Weaver (10.1016/j.jpdc.2024.104904_br0160) 2001 Reddy (10.1016/j.jpdc.2024.104904_br0250) 2016 Abdelaziz (10.1016/j.jpdc.2024.104904_br0470) 2010; 80 Murali (10.1016/j.jpdc.2024.104904_br0340) 2006 Peng (10.1016/j.jpdc.2024.104904_br0060) 2009 Bogdan (10.1016/j.jpdc.2024.104904_br0090) 2007 Khalili (10.1016/j.jpdc.2024.104904_br0390) 2012 Siddagangappa (10.1016/j.jpdc.2024.104904_br0040) 2022 Xue (10.1016/j.jpdc.2024.104904_br0130) 2016 Chou (10.1016/j.jpdc.2024.104904_br0380) 2011 Reddy (10.1016/j.jpdc.2024.104904_br0260) 2015 Zhang (10.1016/j.jpdc.2024.104904_br0410) 2007; 12 Bogdan (10.1016/j.jpdc.2024.104904_br0080) 2011; 30 Chang (10.1016/j.jpdc.2024.104904_br0190) 2011 Khalili (10.1016/j.jpdc.2024.104904_br0370) 2013; 7 Xue (10.1016/j.jpdc.2024.104904_br0110) 2015  | 
    
| References_xml | – volume: 80 start-page: 943 year: 2010 end-page: 953 ident: br0470 article-title: Distribution system reconfiguration using a modified Tabu Search algorithm publication-title: Electr. Power Syst. Res. – volume: 16 start-page: 1 year: 2017 end-page: 10 ident: br0400 article-title: High-performance and energy-efficient fault-tolerance core mapping in NoC publication-title: Sustain. Comput. Inform. Syst. – start-page: 891 year: 2008 end-page: 896 ident: br0230 article-title: Defect tolerance in homogeneous manycore processors using core-level redundancy with unified topology publication-title: Proc. Des. Autom. Test Eur. DATE – start-page: 431 year: 2011 end-page: 436 ident: br0190 article-title: On the design and analysis of fault tolerant NoC architecture using spare routers publication-title: Proc. Proc. Asia South Pac. Des. Autom. Conf. – start-page: 673 year: 2011 end-page: 678 ident: br0380 article-title: FARM: fault-aware resource management in NoC-based multiprocessor platforms publication-title: Proc. Des. Autom. Test Eur. DATE – start-page: 441 year: 2008 end-page: 446 ident: br0180 article-title: A reconfigurable routing algorithm for a fault-tolerant 2D-mesh network-on-chip publication-title: Proc. Proc. Des. Autom. Conf. – start-page: 192 year: 2004 end-page: 195 ident: br0020 article-title: Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs publication-title: Proc. ACM Great Lakes Symp. VLSI – volume: 64 start-page: 2926 year: 2015 end-page: 2939 ident: br0300 article-title: Reconfiguring three-dimensional processor arrays for fault-tolerance: hardness and heuristic algorithms publication-title: IEEE Trans. Comput. – volume: 70 start-page: 950 year: 2021 end-page: 962 ident: br0120 article-title: Plasticity-on-chip design: exploiting self-similarity for data communications publication-title: IEEE Trans. Comput. – start-page: 3 year: 2008 end-page: 22 ident: br0140 article-title: Fault Tolerant Design: An Introduction – start-page: 411 year: 2001 end-page: 420 ident: br0160 article-title: A fault tolerant approach to microprocessor design publication-title: Proc. Intern. Conf. Depend. Sys. Networks – start-page: 1 year: 2015 end-page: 8 ident: br0110 article-title: User cooperation network coding approach for NoC performance improvement publication-title: Proc. IEEE/ACM Int. Symp. Networks-Chip – volume: 7 start-page: 238 year: 2013 end-page: 245 ident: br0370 article-title: A fault-tolerant core mapping technique in networks-on-chip publication-title: IET Comput. Digit. Tech. – start-page: 48 year: 2015 end-page: 53 ident: br0350 article-title: A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architectures publication-title: Proc. Asia South Pac. Des. Autom. Conf. – start-page: 21 year: 2015 end-page: 24 ident: br0260 article-title: Communication energy constrained spare core on NoC publication-title: Proc. Conf. Ph.D. Res. Microelectron. Electron. – volume: 39 start-page: 267 year: 2020 end-page: 271 ident: br0290 article-title: Efficient reconfiguration algorithm with flexible rerouting schemes for constructing 3-D VLSI subarrays publication-title: IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. – start-page: 838 year: 2015 end-page: 845 ident: br0450 article-title: A memetic algorithm for the quadratic assignment problem with parallel local search publication-title: Proc. IEEE Congr. Evol. Comput., CEC - Proc. – volume: 28 year: 2019 ident: br0420 article-title: Algorithms for reconfiguring NoC-based fault-tolerant multiprocessor arrays publication-title: J. Circuits Syst. Comput. – volume: 30 start-page: 1197 year: 2011 end-page: 1210 ident: br0080 article-title: Hitting time analysis for fault-tolerant communication at nanoscale in future multiprocessor platforms publication-title: IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. – start-page: 1 year: 2016 end-page: 8 ident: br0130 article-title: Improving NoC performance under spatio-temporal variability by runtime reconfiguration: a general mathematical framework publication-title: IEEE/ACM Int. Symp. Networks-on-Chip – start-page: 873 year: 2013 end-page: 880 ident: br0240 article-title: An efficient topology reconfiguration algorithm for NoC based multiprocessor arrays publication-title: Proc. - IEEE Int. Conf. High Perform. Comput. Commun., HPCC IEEE Int. Conf. Embedded Ubiquitous Comput. – start-page: 1049 year: 2020 end-page: 1066 ident: br0070 article-title: Fault-tolerant and congestion balanced routing algorithm for 2D mesh NoCs publication-title: Int. J. Web Eng. Technol. – start-page: 195 year: 2021 end-page: 225 ident: br0010 article-title: Network-on-chip (NoC): the technology that enabled multi-processor systems-on-chip (MPSoCs) publication-title: Multi-Processor System-on-Chip 1: Architectures – volume: 9 start-page: 45935 year: 2021 end-page: 45954 ident: br0270 article-title: Flexible spare core placement in torus topology based NoCs and its validation on an FPGA publication-title: IEEE Access – volume: 158 start-page: 176 year: 2021 end-page: 185 ident: br0310 article-title: A high-performance VLSI array reconfiguration scheme based on network flow under row and column rerouting publication-title: J. Parallel Distrib. Comput. – volume: 59 start-page: 482 year: 2013 end-page: 491 ident: br0210 article-title: A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration publication-title: J. Syst. Archit. – volume: 74 start-page: 3026 year: 2014 end-page: 3036 ident: br0320 article-title: Flexible rerouting schemes for reconfiguration of multiprocessor arrays publication-title: J. Parallel Distrib. Comput. – start-page: 157 year: 2009 end-page: 163 ident: br0060 article-title: On soft error rate analysis of scaled CMOS designs: a statistical perspective publication-title: Proc. IEEE ACM Int. Conf. Comput. Des. Dig. Tech. Pap. ICCAD – volume: 10 start-page: 537 year: 2022 end-page: 548 ident: br0050 article-title: HREN: a hybrid reliable and energy-efficient network-on-chip architecture publication-title: IEEE Trans. Emerg. Top. Comput. – start-page: 421 year: 2012 end-page: 428 ident: br0390 article-title: A fault-tolerant low-energy multi-application mapping onto NoC-based multiprocessors publication-title: Proc. - IEEE Int. Conf. Computat. Sci. Eng., CSE IEEE/IFIP Int. Conf. Embedded Ubiquitous Comput. – volume: 30 start-page: 95 year: 2005 end-page: 111 ident: br0480 article-title: A tabu search algorithm for the quadratic assignment problem publication-title: Comput. Optim. Appl. – volume: 2 start-page: 1 year: 2012 end-page: 14 ident: br0460 article-title: Memetic algorithms and memetic computing optimization: a literature review publication-title: Swarm Evol. Comput. – volume: 17 start-page: 1173 year: 2009 end-page: 1186 ident: br0220 article-title: On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems publication-title: IEEE Trans. Very Large Scale Integr. (VLSI) Syst. – start-page: 84 year: 2022 end-page: 92 ident: br0040 article-title: Asynchronous NoC with fault tolerant mechanism: a comprehensive review publication-title: Proc. Int. Conf. Trends Electr., Electron. Comput. Eng. – year: 2007 ident: br0090 article-title: Stochastic communication: a new paradigm for fault-tolerant networks-on-chip publication-title: VLSI Des. – start-page: 169 year: 2023 end-page: 241 ident: br0150 article-title: Fault-tolerant network-on-chip publication-title: Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design: A Self-Test, Self-Diagnosis, and Self-Repair-Based Approach – volume: 5 year: 2016 ident: br0360 article-title: Survey on performance and energy consumption of fault tolerance in network on chip publication-title: Int. J. Embed. Syst. – start-page: 146 year: 2016 end-page: 151 ident: br0250 article-title: A gracefully degrading and energy-efficient fault tolerant NoC using spare core publication-title: Proc. IEEE Comput. Soc. Annu. Symp., on VLSI – volume: 9 start-page: 107625 year: 2021 end-page: 107656 ident: br0030 article-title: A survey on the security of wired, wireless, and 3D network-on-chips publication-title: IEEE Access – year: 2022 ident: br0280 article-title: A survey of fault models and fault tolerance methods for 2D bus-based multi-core systems and TSV based 3D NOC many-core systems – start-page: 1601 year: 2013 end-page: 1604 ident: br0200 article-title: Fault-tolerant routing algorithm for 3D NoC using hamiltonian path strategy publication-title: Proc. Des. Autom. Test Eur. DATE – start-page: 241 year: 2010 end-page: 248 ident: br0440 article-title: QuaLe: a quantum-leap inspired model for non-stationary analysis of NoC traffic in chip multi-processors publication-title: Proc. ACM/IEEE Int. Symp. Networks-on-Chip – volume: 12 start-page: 169 year: 2007 end-page: 174 ident: br0410 article-title: Fault tolerance mechanism in chip many-core processors publication-title: Tsinghua Sci. Technol. – start-page: 160 year: 2005 end-page: 171 ident: br0170 article-title: Rescue: a microarchitecture for testability and defect tolerance publication-title: Proc. Int. Symp. Comput. Archit. – start-page: 161 year: 2012 end-page: 170 ident: br0100 article-title: A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture publication-title: Proc. ACM Int. Conf. Hardw./Softw.-Codesign Syst. Synth. – year: 2006 ident: br0330 article-title: VLSI Test Principles and Architectures: Design for Testability – start-page: 849 year: 2006 end-page: 852 ident: br0430 article-title: DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip publication-title: Proc. Proc. Des. Autom. Conf. – start-page: 845 year: 2006 end-page: 848 ident: br0340 article-title: A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip publication-title: Proc. Proc. Des. Autom. Conf. – volume: 30 start-page: 1197 issue: 8 year: 2011 ident: 10.1016/j.jpdc.2024.104904_br0080 article-title: Hitting time analysis for fault-tolerant communication at nanoscale in future multiprocessor platforms publication-title: IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. doi: 10.1109/TCAD.2011.2138430 – volume: 30 start-page: 95 year: 2005 ident: 10.1016/j.jpdc.2024.104904_br0480 article-title: A tabu search algorithm for the quadratic assignment problem publication-title: Comput. Optim. Appl. doi: 10.1007/s10589-005-4562-x – start-page: 84 year: 2022 ident: 10.1016/j.jpdc.2024.104904_br0040 article-title: Asynchronous NoC with fault tolerant mechanism: a comprehensive review – start-page: 849 year: 2006 ident: 10.1016/j.jpdc.2024.104904_br0430 article-title: DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip – ident: 10.1016/j.jpdc.2024.104904_br0280 – volume: 10 start-page: 537 issue: 2 year: 2022 ident: 10.1016/j.jpdc.2024.104904_br0050 article-title: HREN: a hybrid reliable and energy-efficient network-on-chip architecture publication-title: IEEE Trans. Emerg. Top. Comput. – volume: 59 start-page: 482 issue: 7 year: 2013 ident: 10.1016/j.jpdc.2024.104904_br0210 article-title: A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration publication-title: J. Syst. Archit. doi: 10.1016/j.sysarc.2013.03.010 – year: 2006 ident: 10.1016/j.jpdc.2024.104904_br0330 – volume: 74 start-page: 3026 issue: 10 year: 2014 ident: 10.1016/j.jpdc.2024.104904_br0320 article-title: Flexible rerouting schemes for reconfiguration of multiprocessor arrays publication-title: J. Parallel Distrib. Comput. doi: 10.1016/j.jpdc.2014.06.009 – start-page: 411 year: 2001 ident: 10.1016/j.jpdc.2024.104904_br0160 article-title: A fault tolerant approach to microprocessor design – start-page: 1049 year: 2020 ident: 10.1016/j.jpdc.2024.104904_br0070 article-title: Fault-tolerant and congestion balanced routing algorithm for 2D mesh NoCs publication-title: Int. J. Web Eng. Technol. – start-page: 1601 year: 2013 ident: 10.1016/j.jpdc.2024.104904_br0200 article-title: Fault-tolerant routing algorithm for 3D NoC using hamiltonian path strategy – start-page: 192 year: 2004 ident: 10.1016/j.jpdc.2024.104904_br0020 article-title: Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs – start-page: 21 year: 2015 ident: 10.1016/j.jpdc.2024.104904_br0260 article-title: Communication energy constrained spare core on NoC – volume: 64 start-page: 2926 issue: 10 year: 2015 ident: 10.1016/j.jpdc.2024.104904_br0300 article-title: Reconfiguring three-dimensional processor arrays for fault-tolerance: hardness and heuristic algorithms publication-title: IEEE Trans. Comput. doi: 10.1109/TC.2015.2389846 – volume: 5 issue: 1 year: 2016 ident: 10.1016/j.jpdc.2024.104904_br0360 article-title: Survey on performance and energy consumption of fault tolerance in network on chip publication-title: Int. J. Embed. Syst. – volume: 158 start-page: 176 year: 2021 ident: 10.1016/j.jpdc.2024.104904_br0310 article-title: A high-performance VLSI array reconfiguration scheme based on network flow under row and column rerouting publication-title: J. Parallel Distrib. Comput. doi: 10.1016/j.jpdc.2021.08.005 – volume: 9 start-page: 45935 year: 2021 ident: 10.1016/j.jpdc.2024.104904_br0270 article-title: Flexible spare core placement in torus topology based NoCs and its validation on an FPGA publication-title: IEEE Access doi: 10.1109/ACCESS.2021.3066537 – start-page: 160 year: 2005 ident: 10.1016/j.jpdc.2024.104904_br0170 article-title: Rescue: a microarchitecture for testability and defect tolerance – start-page: 169 year: 2023 ident: 10.1016/j.jpdc.2024.104904_br0150 article-title: Fault-tolerant network-on-chip – start-page: 441 year: 2008 ident: 10.1016/j.jpdc.2024.104904_br0180 article-title: A reconfigurable routing algorithm for a fault-tolerant 2D-mesh network-on-chip – volume: 7 start-page: 238 issue: 6 year: 2013 ident: 10.1016/j.jpdc.2024.104904_br0370 article-title: A fault-tolerant core mapping technique in networks-on-chip publication-title: IET Comput. Digit. Tech. doi: 10.1049/iet-cdt.2013.0032 – volume: 16 start-page: 1 year: 2017 ident: 10.1016/j.jpdc.2024.104904_br0400 article-title: High-performance and energy-efficient fault-tolerance core mapping in NoC publication-title: Sustain. Comput. Inform. Syst. – start-page: 157 year: 2009 ident: 10.1016/j.jpdc.2024.104904_br0060 article-title: On soft error rate analysis of scaled CMOS designs: a statistical perspective – start-page: 838 year: 2015 ident: 10.1016/j.jpdc.2024.104904_br0450 article-title: A memetic algorithm for the quadratic assignment problem with parallel local search – start-page: 241 year: 2010 ident: 10.1016/j.jpdc.2024.104904_br0440 article-title: QuaLe: a quantum-leap inspired model for non-stationary analysis of NoC traffic in chip multi-processors – volume: 39 start-page: 267 issue: 1 year: 2020 ident: 10.1016/j.jpdc.2024.104904_br0290 article-title: Efficient reconfiguration algorithm with flexible rerouting schemes for constructing 3-D VLSI subarrays publication-title: IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. doi: 10.1109/TCAD.2019.2891984 – volume: 70 start-page: 950 issue: 6 year: 2021 ident: 10.1016/j.jpdc.2024.104904_br0120 article-title: Plasticity-on-chip design: exploiting self-similarity for data communications publication-title: IEEE Trans. Comput. doi: 10.1109/TC.2021.3071507 – volume: 12 start-page: 169 issue: S1 year: 2007 ident: 10.1016/j.jpdc.2024.104904_br0410 article-title: Fault tolerance mechanism in chip many-core processors publication-title: Tsinghua Sci. Technol. doi: 10.1016/S1007-0214(07)70104-9 – start-page: 3 year: 2008 ident: 10.1016/j.jpdc.2024.104904_br0140 – start-page: 1 year: 2015 ident: 10.1016/j.jpdc.2024.104904_br0110 article-title: User cooperation network coding approach for NoC performance improvement – start-page: 873 year: 2013 ident: 10.1016/j.jpdc.2024.104904_br0240 article-title: An efficient topology reconfiguration algorithm for NoC based multiprocessor arrays – start-page: 891 year: 2008 ident: 10.1016/j.jpdc.2024.104904_br0230 article-title: Defect tolerance in homogeneous manycore processors using core-level redundancy with unified topology – volume: 2 start-page: 1 year: 2012 ident: 10.1016/j.jpdc.2024.104904_br0460 article-title: Memetic algorithms and memetic computing optimization: a literature review publication-title: Swarm Evol. Comput. doi: 10.1016/j.swevo.2011.11.003 – start-page: 146 year: 2016 ident: 10.1016/j.jpdc.2024.104904_br0250 article-title: A gracefully degrading and energy-efficient fault tolerant NoC using spare core – start-page: 161 year: 2012 ident: 10.1016/j.jpdc.2024.104904_br0100 article-title: A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture – start-page: 195 year: 2021 ident: 10.1016/j.jpdc.2024.104904_br0010 article-title: Network-on-chip (NoC): the technology that enabled multi-processor systems-on-chip (MPSoCs) – volume: 80 start-page: 943 issue: 8 year: 2010 ident: 10.1016/j.jpdc.2024.104904_br0470 article-title: Distribution system reconfiguration using a modified Tabu Search algorithm publication-title: Electr. Power Syst. Res. doi: 10.1016/j.epsr.2010.01.001 – start-page: 1 year: 2016 ident: 10.1016/j.jpdc.2024.104904_br0130 article-title: Improving NoC performance under spatio-temporal variability by runtime reconfiguration: a general mathematical framework publication-title: IEEE/ACM Int. Symp. Networks-on-Chip – year: 2007 ident: 10.1016/j.jpdc.2024.104904_br0090 article-title: Stochastic communication: a new paradigm for fault-tolerant networks-on-chip publication-title: VLSI Des. doi: 10.1155/2007/95348 – volume: 28 issue: 7 year: 2019 ident: 10.1016/j.jpdc.2024.104904_br0420 article-title: Algorithms for reconfiguring NoC-based fault-tolerant multiprocessor arrays publication-title: J. Circuits Syst. Comput. doi: 10.1142/S0218126619501111 – start-page: 48 year: 2015 ident: 10.1016/j.jpdc.2024.104904_br0350 article-title: A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architectures – start-page: 845 year: 2006 ident: 10.1016/j.jpdc.2024.104904_br0340 article-title: A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip – volume: 17 start-page: 1173 issue: 9 year: 2009 ident: 10.1016/j.jpdc.2024.104904_br0220 article-title: On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems publication-title: IEEE Trans. Very Large Scale Integr. (VLSI) Syst. doi: 10.1109/TVLSI.2008.2002108 – start-page: 673 year: 2011 ident: 10.1016/j.jpdc.2024.104904_br0380 article-title: FARM: fault-aware resource management in NoC-based multiprocessor platforms – start-page: 431 year: 2011 ident: 10.1016/j.jpdc.2024.104904_br0190 article-title: On the design and analysis of fault tolerant NoC architecture using spare routers – start-page: 421 year: 2012 ident: 10.1016/j.jpdc.2024.104904_br0390 article-title: A fault-tolerant low-energy multi-application mapping onto NoC-based multiprocessors – volume: 9 start-page: 107625 year: 2021 ident: 10.1016/j.jpdc.2024.104904_br0030 article-title: A survey on the security of wired, wireless, and 3D network-on-chips publication-title: IEEE Access doi: 10.1109/ACCESS.2021.3100540  | 
    
| SSID | ssj0011578 | 
    
| Score | 2.4043293 | 
    
| Snippet | In multi-core processor systems, the Network-on-Chip (NoC) serves as a vital communication infrastructure. To ensure chip reliability during potential... | 
    
| SourceID | crossref elsevier  | 
    
| SourceType | Index Database Publisher  | 
    
| StartPage | 104904 | 
    
| SubjectTerms | Algorithm Core-level redundancy Fault-tolerant Multiprocessor array Network on chip Topology reconfiguration  | 
    
| Title | Efficient topology reconfiguration for NoC-based multiprocessors: A greedy-memetic algorithm | 
    
| URI | https://dx.doi.org/10.1016/j.jpdc.2024.104904 | 
    
| Volume | 190 | 
    
| hasFullText | 1 | 
    
| inHoldings | 1 | 
    
| isFullTextHit | |
| isPrint | |
| journalDatabaseRights | – providerCode: PRVESC databaseName: Baden-Württemberg Complete Freedom Collection (Elsevier) customDbUrl: eissn: 1096-0848 dateEnd: 99991231 omitProxy: true ssIdentifier: ssj0011578 issn: 0743-7315 databaseCode: GBLVA dateStart: 20110101 isFulltext: true titleUrlDefault: https://www.sciencedirect.com providerName: Elsevier – providerCode: PRVESC databaseName: Elsevier Science Direct Journals customDbUrl: eissn: 1096-0848 dateEnd: 99991231 omitProxy: true ssIdentifier: ssj0011578 issn: 0743-7315 databaseCode: AIKHN dateStart: 19950101 isFulltext: true titleUrlDefault: https://www.sciencedirect.com providerName: Elsevier – providerCode: PRVESC databaseName: Elsevier ScienceDirect customDbUrl: eissn: 1096-0848 dateEnd: 99991231 omitProxy: true ssIdentifier: ssj0011578 issn: 0743-7315 databaseCode: .~1 dateStart: 19950101 isFulltext: true titleUrlDefault: https://www.sciencedirect.com providerName: Elsevier – providerCode: PRVESC databaseName: Elsevier SD Complete Freedom Collection [SCCMFC] customDbUrl: eissn: 1096-0848 dateEnd: 99991231 omitProxy: true ssIdentifier: ssj0011578 issn: 0743-7315 databaseCode: ACRLP dateStart: 19950101 isFulltext: true titleUrlDefault: https://www.sciencedirect.com providerName: Elsevier – providerCode: PRVLSH databaseName: Elsevier Journals customDbUrl: mediaType: online eissn: 1096-0848 dateEnd: 99991231 omitProxy: true ssIdentifier: ssj0011578 issn: 0743-7315 databaseCode: AKRWK dateStart: 19840801 isFulltext: true providerName: Library Specific Holdings  | 
    
| link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwnV1NS8NAEB1KvXjxW2zVsgdvEpsm2Xx4K6WlKvSihR6EkGR3a4ptSk0PXvztzmQ3oggePCZkIcwmM2-S994AXAUk1uxJZZGIk75WOZQHA8uJbIFwREns5ohtMfHHU-9-xmcNGNRaGKJVmtyvc3qVrc2Zrolmd53n3UcqfoGL9cezK6EDKdi9gKYY3Hx80TzISyasrTjpaiOc0RyvxVqQjaHj0a_OyAxr-1WcvhWc0QHsGaTI-vpmDqEhV0ewX09hYOalPIbnYeUCgcWDlXriwTur2lyVz7d6fxkiUzYpBhbVLME0iVArBIrN2y3rM-y6Md1aS7kkUSNLXufFJi9flicwHQ2fBmPLzEywMkQqpZU4EUGghOZRKd_PyPDOToUThV7KlRMkrgoRAyrX7fWyhAcOQgQy1XM9Eblc-O4pNFfFSp4BC1MuqB3zEeF5uJOJQjQhbJ7JQCVS-C24roMVr7U1RlxzxhYxhTam0MY6tC3gdTzjHxscY-7-Y137n-vOYZeONFfvAprlZisvET-Uaad6QDqw0797GE8-AcVawr0 | 
    
| linkProvider | Elsevier | 
    
| linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwnV09T8MwED2VMsDCN6J8emBDoakT54OtqooKlC60UgckK4njkoo2VUkHFn47vthBICQG1iSWonNy9y557x3ApY9izVYqLRRx4tcqinnQt2hoCwVHZKq6OWRbDLzeyL0fs3ENOpUWBmmVJvfrnF5ma3OkaaLZXGRZ8wmLn--o-uPapdBhDdZdRn3swK4_vngeaCYTVF6ceLlRzmiS13Qh0MeQuvivMzTT2n5Vp28V53YHtgxUJG19N7tQS-d7sF2NYSDmrdyH525pA6GqByn0yIN3Uva5Mpus9AYTBU3JIO9YWLQE0SxCLRHIl283pE1U263yrTVLZ6hqJNHrJF9mxcvsAEa33WGnZ5mhCVaioEphRTREDBThQCrpeQk63tmxoGHgxkxSP3JkoECgdJxWK4mYTxVGQFc9xxWhw4TnHEJ9ns_TIyBBzAT2Y56CeK7aykgqOCFslqS-jFLhNeCqChZfaG8MXpHGphxDyzG0XIe2AayKJ_-xw1wl7z_WHf9z3QVs9IaPfd6_GzycwCae0cS9U6gXy1V6psBEEZ-XD8snhoHEUg | 
    
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Efficient+topology+reconfiguration+for+NoC-based+multiprocessors%3A+A+greedy-memetic+algorithm&rft.jtitle=Journal+of+parallel+and+distributed+computing&rft.au=Qian%2C+Junyan&rft.au=Zhang%2C+Chuanfang&rft.au=Wu%2C+Zheng&rft.au=Ding%2C+Hao&rft.date=2024-08-01&rft.issn=0743-7315&rft.volume=190&rft.spage=104904&rft_id=info:doi/10.1016%2Fj.jpdc.2024.104904&rft.externalDBID=n%2Fa&rft.externalDocID=10_1016_j_jpdc_2024_104904 | 
    
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=0743-7315&client=summon | 
    
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=0743-7315&client=summon | 
    
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=0743-7315&client=summon |