A 94.3-dB SNDR 184-dB FoMs 4th-Order Noise-Shaping SAR ADC With Dynamic-Amplifier-Assisted Cascaded Integrator

• Published in: IEEE solid-state circuits letters Vol. 8; pp. 65 - 68
• Main Authors: Cheng, Kai-Cheng, Chang, Soon-Jyh, Chen, Chung-Chieh, Hung, Shuo-Hong
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 2025; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Amplifiers; Analog to digital converters; Analog-to-digital converter (ADC); Bandwidth; Capacitors; Electric potential; Figure of merit; Integrators; Noise; Noise levels; Noise shaping; noise shaping (NS); oversampling; Power demand; Semiconductor device measurement; sigma-delta (SD) ADC; Solid state circuits; successive approximation register (SAR) ADC; Switches; Temperature measurement; Voltage; Voltage measurement
• ISSN: 2573-9603; 2573-9603
• DOI: 10.1109/LSSC.2025.3544649

This letter presents a fully dynamic 4th-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with the proposed 4th-order cascaded integrator using dynamic-amplifier-assisted and passive integration. This ADC can achieve sharp NTF with only two dynamic amplifiers and is insensitive to process, voltage, and temperature (PVT) variation. The NS-SAR ADC occupies 0.09 mm2 in a 28-nm CMOS process. With a 1-V supply voltage, it consumes <inline-formula> <tex-math notation="LaTeX">107.38~\mu </tex-math></inline-formula>W at 5 MS/s. The measured signal-to-noise and distortion ratio (SNDR) is 94.3 dB over a 100-kHz bandwidth (BW), resulting in a Schreier figure of merit (FoM) of 184 dB and a Walden FoM of 12.6 fJ/conv.-step.