UFBBR: A Unified Frequency and Back-Bias Regulation Unit for Ultralow-Power Microcontrollers in 28-nm FDSOI

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 70; no. 6; pp. 1 - 14
• Main Authors: Schramme, Maxime, Bol, David
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Actuation; Adaptive back biasing (ABB); and temperature (PVT) compensation; Bias; Charge pumps; clock generation; Clocks; Delays; Frequency locking; frequency-locked loop (FLL); fully-depleted silicon-on-insulator (FDSOI); Knobs; microcontroller unit (MCU); Microcontrollers; Oscillators; Power consumption; process; Regulation; ring oscillator (RO); Sensors; Silicon-on-insulator; switched-capacitor charge-pump (SCCP); Temperature sensors; ultralow power (ULP); ultralow voltage (ULV); voltage; Voltage control; Voltage reduction
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2023.3257270

Sensitivity to process, voltage, and temperature (PVT) variations constitutes a serious obstacle in ultralow-voltage/ultralow-power (ULV/ULP) circuits and systems. To address this challenge, we propose a unified frequency/back-bias regulation (UFBBR) macro embedded in a custom ULP ARM Cortex-M4 microcontroller unit (MCU) manufactured in 28-nm FDSOI technology. The UFBBR technique combines the generation of a 32-to-80 MHz system clock and asymmetric adaptive back biasing for PVT compensation. Relying on a novel dual-output frequency-locked loop, it senses both the logic speed and the N/PMOS process imbalance using back-bias-controlled oscillators, and generates adequate forward back-bias voltages with digitally-controlled oscillators followed by switched-capacitor charge-pumps for fast current actuation. Compared to a situation with zero back biasing and appropriate frequency/voltage margins, the UFBBR provides 15<inline-formula> <tex-math notation="LaTeX">\times</tex-math> </inline-formula> of frequency boosting at 0.4 V or 180 mV of voltage reduction at 64 MHz. It leverages software-programmable configuration knobs to achieve a fast wake-up of 8 <inline-formula> <tex-math notation="LaTeX">\upmu</tex-math> </inline-formula>s and an in-lock power of 22 <inline-formula> <tex-math notation="LaTeX">\upmu</tex-math> </inline-formula>W, with an area overhead below 0.032 mm 2 . In sleep, it drives the back-bias voltages towards 0 V and disables the clock for minimum power consumption. These features help the MCU system achieve a minimum energy point of 5.5 <inline-formula> <tex-math notation="LaTeX">\upmu</tex-math> </inline-formula>W/MHz and a sleep power of 7.7 <inline-formula> <tex-math notation="LaTeX">\upmu</tex-math> </inline-formula>W.