Dynamic Precision-Scalable Thermal Mapping Algorithm for Three Dimensional Systolic-Array Based Neural Network Accelerator

Nowadays, the systolic-array based accelerator has been used widely for the neural-network applications. Multiple systolic-array based accelerator chips can be stacked by the 3D IC technology to improve the performance of the neural-network applications. However, the 3D accelerator increases the pow...

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Published inIEEE transactions on consumer electronics Vol. 70; no. 1; pp. 757 - 769
Main Authors Lin, Shu-Yen, Tsai, Chun-Kuan, Kao, Wen-Chun
Format Journal Article
LanguageEnglish
Published New York IEEE 01.02.2024
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
accelerator
Algorithms
Arrays
Artificial neural networks
Density measurement
Heuristic algorithms
Integrated circuits
Neural network
Neural networks
Overheating
Performance enhancement
Power system measurements
Stacking
Temperature distribution
Thermal mapping
Three-dimensional displays
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ISSN0098-3063
1558-4127
DOI10.1109/TCE.2024.3378706

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Abstract Nowadays, the systolic-array based accelerator has been used widely for the neural-network applications. Multiple systolic-array based accelerator chips can be stacked by the 3D IC technology to improve the performance of the neural-network applications. However, the 3D accelerator increases the power density and causes the overheating. To avoid the overheating, the sacrifice of the performance for the 3D accelerator under the thermal limitations is important. In this work, a dynamic precision-scalable thermal mapping algorithm (DPSTM) is proposed to change the active processing elements with different data precisions in the 3D accelerators dynamically. The goal is to control the power density and peak temperature of the 3D accelerator. Compared with the related works, DPSTM can reduce 29%-77% and 7%-73% latencies in AlexNet and ResNet-18 with 92-95°C thermal limitations.
AbstractList Nowadays, the systolic-array based accelerator has been used widely for the neural-network applications. Multiple systolic-array based accelerator chips can be stacked by the 3D IC technology to improve the performance of the neural-network applications. However, the 3D accelerator increases the power density and causes the overheating. To avoid the overheating, the sacrifice of the performance for the 3D accelerator under the thermal limitations is important. In this work, a dynamic precision-scalable thermal mapping algorithm (DPSTM) is proposed to change the active processing elements with different data precisions in the 3D accelerators dynamically. The goal is to control the power density and peak temperature of the 3D accelerator. Compared with the related works, DPSTM can reduce 29%-77% and 7%-73% latencies in AlexNet and ResNet-18 with 92-95°C thermal limitations.
Author Tsai, Chun-Kuan
Kao, Wen-Chun
Lin, Shu-Yen
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Snippet Nowadays, the systolic-array based accelerator has been used widely for the neural-network applications. Multiple systolic-array based accelerator chips can be...
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SubjectTerms accelerator
Algorithms
Arrays
Artificial neural networks
Density measurement
Heuristic algorithms
Integrated circuits
Neural network
Neural networks
Overheating
Performance enhancement
Power system measurements
Stacking
Temperature distribution
Thermal mapping
Three-dimensional displays
Title Dynamic Precision-Scalable Thermal Mapping Algorithm for Three Dimensional Systolic-Array Based Neural Network Accelerator
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Volume 70
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