FPGA implementation of feature detection and matching using ORB
Oriented FAST and Rotated BRIEF (ORB) is becoming the method of choice in real-time feature matching applications by offering performances comparable to other state-of-the-art descriptors at a fraction of the runtime and memory requirements. These characteristics have prompted multiple researchers t...
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| Published in | Microprocessors and microsystems Vol. 94; p. 104666 |
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| Main Authors | , , |
| Format | Journal Article |
| Language | English |
| Published |
Elsevier B.V
01.10.2022
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| Subjects | |
| Online Access | Get full text |
| ISSN | 0141-9331 1872-9436 |
| DOI | 10.1016/j.micpro.2022.104666 |
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| Abstract | Oriented FAST and Rotated BRIEF (ORB) is becoming the method of choice in real-time feature matching applications by offering performances comparable to other state-of-the-art descriptors at a fraction of the runtime and memory requirements. These characteristics have prompted multiple researchers to propose FPGA-based accelerators that allow for a significant increase in throughput compared to general-purpose processors. This increase is, however, achieved at the expense of the descriptor’s robustness as several approximations are necessary to map the algorithm efficiently into hardware which negatively affects its invariance. In this paper, we introduce an FPGA architecture capable of extracting ORB descriptors at high throughput with minimal impact to their invariance. Rotation of sample point coordinates is bypassed entirely, and methods for the accurate computation of the moments and descriptor generation in a single clock cycle are described. Moreover, a feature matching algorithm based on the cross-check criterion is proposed and implemented in hardware. The architecture achieved a throughput of 94 MPix/s using a 100 MHz clock while producing an almost identical performance compared to the reference implementation.
•An FPGA-based accelerator of the ORB descriptor is proposed.•Methods for the accurate computation of the patch moments are described.•Rotation of sample point coordinates is bypassed.•The descriptor is computed in a single clock cycle.•Feature matching using the cross-check criterion has been implemented in hardware. |
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| AbstractList | Oriented FAST and Rotated BRIEF (ORB) is becoming the method of choice in real-time feature matching applications by offering performances comparable to other state-of-the-art descriptors at a fraction of the runtime and memory requirements. These characteristics have prompted multiple researchers to propose FPGA-based accelerators that allow for a significant increase in throughput compared to general-purpose processors. This increase is, however, achieved at the expense of the descriptor’s robustness as several approximations are necessary to map the algorithm efficiently into hardware which negatively affects its invariance. In this paper, we introduce an FPGA architecture capable of extracting ORB descriptors at high throughput with minimal impact to their invariance. Rotation of sample point coordinates is bypassed entirely, and methods for the accurate computation of the moments and descriptor generation in a single clock cycle are described. Moreover, a feature matching algorithm based on the cross-check criterion is proposed and implemented in hardware. The architecture achieved a throughput of 94 MPix/s using a 100 MHz clock while producing an almost identical performance compared to the reference implementation.
•An FPGA-based accelerator of the ORB descriptor is proposed.•Methods for the accurate computation of the patch moments are described.•Rotation of sample point coordinates is bypassed.•The descriptor is computed in a single clock cycle.•Feature matching using the cross-check criterion has been implemented in hardware. |
| ArticleNumber | 104666 |
| Author | Bentoutou, Youcef Chikr El-Mezouar, Miloud Belmessaoud, Nadir Mohamed |
| Author_xml | – sequence: 1 givenname: Nadir Mohamed orcidid: 0000-0002-2669-2346 surname: Belmessaoud fullname: Belmessaoud, Nadir Mohamed email: mohamed.belmessaoud@univ-sba.dz organization: RCAM Laboratory, Department of Electronics, Djillali Liabes university, Sidi Bel Abbes, 22084, Sidi Bel Abbes, Algeria – sequence: 2 givenname: Youcef surname: Bentoutou fullname: Bentoutou, Youcef email: bentoutou@asal.dz organization: Satellite Development Center, Algerian Space Agency, Bir El Djir, 31130, Oran, Algeria – sequence: 3 givenname: Miloud surname: Chikr El-Mezouar fullname: Chikr El-Mezouar, Miloud email: miloud.chikrelmezouar@univ-sba.dz organization: RCAM Laboratory, Department of Electronics, Djillali Liabes university, Sidi Bel Abbes, 22084, Sidi Bel Abbes, Algeria |
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| Cites_doi | 10.5201/ipol.2018.229 10.1109/ICCV.2011.6126544 10.1109/iEECON51072.2021.9440232 10.18100/ijamec.60004 10.1109/TENCON.2013.6718842 10.1016/j.cviu.2007.09.014 10.1109/MVA.2015.7153140 10.1109/FPT.2017.8280137 10.1109/BEC.2012.6376874 10.23919/ChiCC.2018.8483513 10.1109/FPT.2017.8280159 10.1109/TVLSI.2018.2881105 10.1109/SSST.2011.5753797 10.1109/ACCESS.2021.3104387 10.5772/61434 10.1109/ICFPT51103.2020.00047 10.1109/ISCAS.2017.8050258 10.1007/s11263-005-3848-x 10.1109/ICSIPA45851.2019.8977793 10.14257/ijca.2014.7.3.20 10.3390/s18041014 10.1023/A:1008199403446 10.1109/TPAMI.2005.188 10.1023/B:VISI.0000029664.99615.94 10.1109/FPL.2014.6927402 |
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| Keywords | Feature matching Feature detection FPGA Oriented FAST and Rotated BRIEF |
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| Title | FPGA implementation of feature detection and matching using ORB |
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