Design of Modified March-C Algorithm and Built-in self-test architecture for Memories

Semiconductor Memories is a pivotal aspect as its technology growth increases. RAM, ROM, DRAM, etc., are the different types of memory and it becomes difficult to test the memory because of the complexity of the design increases day by day. The testing of memory is very difficult as it's requir...

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Bibliographic Details
Published in3C tecnología pp. 219 - 229
Main Authors Karthy, G., Sivakumar, P.
Format Journal Article
LanguageEnglish
Published Alcoy 3Ciencias 01.03.2020
Subjects
Algorithms
Built in test
Computer architecture
Design modifications
Dynamic random access memory
Self tests
Semiconductors
Writing
Online AccessGet full text
ISSN2254-4143
2605-3853
2254-4143
DOI10.17993/3ctecno.2020.specialissue4.219-229

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Summary:Semiconductor Memories is a pivotal aspect as its technology growth increases. RAM, ROM, DRAM, etc., are the different types of memory and it becomes difficult to test the memory because of the complexity of the design increases day by day. The testing of memory is very difficult as it's required many test patterns. In this paper, a new test architecture is designed using a response analyzer and checker to detect a fault on a chip, and the modified MARCH C algorithm is also proposed to check the fault in the memory in the shortest time.
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ISSN:2254-4143
2605-3853
2254-4143
DOI:10.17993/3ctecno.2020.specialissue4.219-229