A 98.1 % CE, 100 mA MLC multi-reference output all digital LDO with fast settling and digital self calibration for DVFS and multi-VDD applications

• Published in: Analog integrated circuits and signal processing Vol. 89; no. 2; pp. 437 - 450
• Main Authors: Kaedi, S., Ghaznavi-Ghoushchi, M. B., Rahimi, M.
• Format: Journal Article
• Language: English
• Published: New York Springer US 01.11.2016; Springer Nature B.V
• Subjects: Access control; Calibration; Circuits; Circuits and Systems; Current efficiency; Electric potential; Electrical Engineering; Engineering; Microprocessors; Self calibration; Settling; Shift registers; Signal,Image and Speech Processing; Voltage; Power management; Current efficiency; Multi level comparator; Multi-reference output all digital LDO; Dynamic voltage and frequency scaling (DVFS); Multi reference supply voltage; ARM1176JZF-S; Low-dropout regulator (LDO)
• ISSN: 0925-1030; 1573-1979
• DOI: 10.1007/s10470-016-0843-9

This paper presents a Multiple Reference All Digital Low Dropout Regulator (MRADLDO) utilized 98.1 % current efficiency and 100 mA maximum load current. MRADLDO performs selectable different reference voltages to apply in the multi VDD core applications as well as Dynamic Voltage and Frequency Scaling issues. This improves control on delay, speed and power of the subject circuits. This structure has the fast response to variation in load or variation in selection voltages. Maximum required time for settling output, in the worst case, is less than 256 ns. Furthermore, a self calibration structure is embedded for the sake of decreasing the steady-state time. While changing the output voltage (V out ), reference voltage (V ref ) is been switched accrued, there is a parallel access to control unit data in order to load initial value for the LDO controller shift registers from a simple embedded memory. To show the effectiveness of the proposed design, it is applied on ARM1176JZF-S processor supply via producing four required levels of voltage as high level (HL)@1.21 V, medium level ML@1.14 V, low level LL@0.99 V and sleep mode SM@0 V. Likewise, a comparison between two proposed multi references LDO such as MRADLDO and analog multiplexer is utilized to illustrate the effectiveness of the proposed MRADLDO circuit.