FPGA‐Based Self‐Calibrating Attention Algorithm for Low‐Light Enhancement and Implementation

• Published in: Concurrency and computation Vol. 37; no. 23-24
• Main Authors: Han, Jin, Jiang, Haoyu
• Format: Journal Article
• Language: English
• Published: Hoboken, USA John Wiley & Sons, Inc 25.10.2025
• Subjects: attention mechanism; hardware‐software co‐optimization; low‐light image enhancement; unsupervised learning
• ISSN: 1532-0626; 1532-0634
• DOI: 10.1002/cpe.70255

ABSTRACT Image enhancement methods in extreme low‐light scenarios face noise amplification, insufficient brightness restoration, and high model complexity. Moreover, existing methods often fail to balance enhancement performance and efficiency on resource‐constrained edge devices. To address these issues, we propose an ASCLE (Attention‐based Self‐Calibrating Low‐light Enhancement) algorithm with FPGA‐based hardware‐software co‐optimization. Building upon a self‐calibrating illumination framework, ASCLE employs an attention mechanism and dual‐path denoising to suppress noise in dark regions while sharpening edge details. An illumination correction module, with a brightness‐aware mask and color fidelity loss constraint, is introduced to address insufficient brightness and color distortion. To reduce computational and storage demands, we employ optimization strategies such as BN layer fusion and approximate activation functions to improve the hardware adaptability of the core modules. For FPGA deployment, tiled computation and ping‐pong double buffering optimize data flow, while parallel pipelining boosts hardware resource use and computational efficiency. Experimental results demonstrate that the ASCLE algorithm achieves PSNR and SSIM scores of 19.88 dB and 0.784 on the LOL dataset, outperforming baseline methods. On FPGA, the inference time for a single frame is 10.64 ms, surpassing that of an Intel i7‐12800HX CPU (1.414 s) and an ARM Cortex‐A9 processor (9.088 s), while system power consumption is reduced to 2.07 W.