A Low-Complexity Soft-Output Massive MIMO Detector With Near-Optimum Performance

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 71; no. 12; pp. 5445 - 5456
• Main Authors: Hu, Jinjie, Song, Suwen, Wang, Zhongfeng
• Format: Journal Article
• Language: English
• Published: IEEE 01.12.2024
• Subjects: Antennas; Complexity theory; coordinate descent; Detectors; Hardware; likelihood ascend; Massive MIMO; Modulation; modulation-based successive gradient descent; Optimization models; soft-output detector; Very large scale integration; VLSI
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2024.3435361

In massive multiple-input multiple-output (MIMO) detection, the likelihood ascent search (LAS) algorithm is well-known for its near-optimum performance and low complexity. It employs gradient descent to enhance the performance of suboptimal MIMO detectors, specifically the minimum mean-square error (MMSE) algorithm. In this paper, we introduce several techniques to improve the MMSE-based LAS (MMSE-LAS) algorithm in terms of both complexity and performance. To reduce complexity, the MMSE is first replaced with the low-complexity optimized coordinate descent (OCD) algorithm at the cost of negligible performance loss. Then, the conventional OCD and LAS algorithms are optimized for better computation reuse. Besides, we derive a new soft-output computation formula for LAS to improve the coded performance. The proposed modulation-based successive gradient descent (MB-SGD) detector outperforms MMSE-LAS and the latest work in terms of either complexity or performance for <inline-formula> <tex-math notation="LaTeX">64\times 8 </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">128\times 8 </tex-math></inline-formula> LDPC-coded MIMO systems with multiple modulations from QPSK to 256-QAM. The corresponding architecture for a <inline-formula> <tex-math notation="LaTeX">128\times 8 </tex-math></inline-formula> coded MIMO system supporting multiple modulations is implemented on a Xilinx Virtex-7 FPGA and with TSMC 28-nm CMOS technology, exhibiting 74.5% lower latency and 0.24 dB gain compared to OCD on FPGA, and also achieving <inline-formula> <tex-math notation="LaTeX">14.59\times </tex-math></inline-formula> energy efficiency and <inline-formula> <tex-math notation="LaTeX">2.04\times </tex-math></inline-formula> area efficiency over the state-of-the-art implementation on ASIC.