Implementation of Polyphase Digital Down Converter Using Optimized LMS Algorithm for WCDMA Application - Datta, Debarshi; Naskar, Mrinal Kanti (IEEE embedded systems letters, 2024)
This letter presents the implementation of a polyphase digital down converter (DDC) that employs a least mean square (LMS) algorithm associated with particle swarm optimization (PSO) for the wideband code division multiple access (WCDMA) application. The PSO-based LMS algorithm suppresses the noise signal, enabling a significant improvement in the spurious-free dynamic range (SFDR), which is 130 dB. The complex multiplication is realized by the canonical impel-mentation to reduce the number of multipliers. The suggested polyphase DDC architecture is successfully implemented in the field-programmable gate array device (FPGA) Kintex-7 platform. To achieve high accuracy, the proposed design is implemented with an efficient user-defined floating-point representation data type. Synthesis results suggested that the design consumes less area and power compared to the most recent structure.