Energy efficient design and implementation of approximate adder for image processing applications

• Published in: Serbian journal of electrical engineering Vol. 22; no. 1; pp. 75 - 92
• Main Authors: Naik, Jatothu, Kumar, Kanagala, Krishnaiah, Kondragunta, Koteswararao, Seelam
• Format: Journal Article
• Language: English
• Published: Faculty of Technical Sciences in Cacak 01.01.2025
• Subjects: adder design; approximate computing; fpga; image addition; image processing
• ISSN: 1451-4869; 2217-7183; 2217-7183
• DOI: 10.2298/SJEE2501075B

Approximate computing is a new technique that promises to speed up computations while preserving a level of precision suitable for error-tolerant systems such as neural networks and graphics. At the edge, a lot of computationally complex methods are now in use. As such, designing quick and low-energy circuits is crucial. This work presents a novel approximate full adder approach that lowers power consumption and delay at the expense of some output mistakes. To achieve these objectives, the proposed full adder architecture makes use of fundamental gate logic reduction techniques. Evaluations based on the Intel FPGA synthesis tool indicate that the suggested adder surpasses state-of-the-art techniques in terms of power, speed, and propagation delay. The design parameters - area, power dissipation, and latent characteristics of proposed adder are verified by simulation using EDA tools. The results demonstrate that our proposed approximate adder runs faster and requires fewer logic components than earlier equivalent systems. The synthesis reports testify to the fact that compared to other adders currently in use, the suggested adder used less logic elements. Furthermore, suggested approximation adders were used to execute image additions. Using image addition, the image quantitative statistics are used to application-level accuracy metrics analysis. Quantitative results confirm the superior functioning of the full adder cell approximation over comparable models.