APA (7th ed.) Citation

Chandrasetty, V. A., & Aziz, S. M. (2011). FPGA Implementation of a LDPC Decoder using a Reduced Complexity Message Passing Algorithm. Journal of networks, 6(1), 36. https://doi.org/10.4304/jnw.6.1.36-45

Chicago Style (17th ed.) Citation

Chandrasetty, Vikram Arkalgud, and Syed Mahfuzul Aziz. "FPGA Implementation of a LDPC Decoder Using a Reduced Complexity Message Passing Algorithm." Journal of Networks 6, no. 1 (2011): 36. https://doi.org/10.4304/jnw.6.1.36-45.

MLA (9th ed.) Citation

Chandrasetty, Vikram Arkalgud, and Syed Mahfuzul Aziz. "FPGA Implementation of a LDPC Decoder Using a Reduced Complexity Message Passing Algorithm." Journal of Networks, vol. 6, no. 1, 2011, p. 36, https://doi.org/10.4304/jnw.6.1.36-45.