Nanoscale MOSFET Modeling: Part 1: The Simplified EKV Model for the Design of Low-Power Analog Circuits

• Published in: IEEE solid state circuits magazine Vol. 9; no. 3; pp. 26 - 35
• Main Authors: Enz, Christian, Chicco, Francesco, Pezzotta, Alessandro
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 01.01.2017; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog circuits; Circuit design; CMOS; CMOS process; Design parameters; Field effect transistors; Integrated circuit modeling; Integrated circuits; Mathematical models; MOSFETs; Resistance; Saturation; Semiconductor device modeling; Semiconductor devices; Silicon; Transconductance; Transistors; Voltage measurement
• ISSN: 1943-0582; 1943-0590
• DOI: 10.1109/MSSC.2017.2712318

This article presents the s implified charge-based Enz-Krummenacher-Vittoz (EKV) [11] metal-oxide-semiconductor field-effect transistor (MOSFET) model and shows that it can be used for advanced complementary metal-oxide-semiconductor (CMOS) processes despite its very few parameters. The concept of an inversion coefficient (IC) is first introduced as an essential design parameter that replaces the overdrive voltage V G -V T0 and spans the entire range of operating points from weak via moderate to strong inversion (SI), including the effect of velocity saturation (VS). The simplified model in saturation is then presented and validated for different 40- and 28-nm bulk CMOS processes. A very simple expression of the normalized transconductance in saturation, valid from weak to SI and requiring only the VS parameter mc, is described. The normalized transconductance efficiency G m /I D , which is a key figure-of-merit (FoM) for the design of low-power analog circuits, is then derived as a function of IC including the effect of VS. It is then successfully validated from weak to SI with data measured on a 40-nm and two 28-nm bulk CMOS processes. It is then shown that the normalized output conductance G ds /I D follows a similar dependence with IC than the normalized G m /I D characteristic but with different parameters accounting for drain induced barrier lowering (DIBL). The methodology for extracting the few parameters from the measured I D -V G and I D -V D characteristics is then detailed. Finally, it is shown that the simplified EKV model can also be used for a fully depleted silicon on insulator (FDSOI) and Fin-FET 28-nm processes.