Recursive least-square algorithm with ud factorization by fixed-point arithmetic - Tsubokawa, Hiroshi; Tsujii, Shigeo; Kubota, Hajime (Electronics & communications in Japan. Part 3, Fundamental electronic science, 1992)
It is known that a recursive least‐square (RLS) algorithm with UD factorization equivalent to the (standard) RLS algorithm can be realized by using the systolic array proposed by Kung. In general, in constructing a special hardware, the wordlength of a processor is related to the arithmetic processing speed and the area of the hardware. Therefore, an important subject is how to shorten the wordlength of processors used in the systolic array executing the RLS method with UD factorization. The authors have already carried out an operational error analysis in finite wordlength floating‐point arithmetic and described that this algorithm can be executed with short arithmetic wordlength. If the algorithm can be executed with short arithmetic wordlength also in the fixed‐point arithmetic, then we can expect improved operational processing speed and simpler hardware structure compared to the special hardware of the floating‐point arithmetic mode. Thus, this paper describes an RLS method by finite wordlength fixed‐point arithmetic with UD factorization and evaluates the operational error. Then the evaluation of convergence values and number of updates of the algorithm are shown analytically. Finally, the appropriateness of theoretical analysis results of convergence values and the number of updates are confirmed by computer simulations.