Transformation and dynamic visualization of images from computer through an FPGA in a matrix of LED

• Published in: Telkomnika Vol. 17; no. 6; pp. 3003 - 3009
• Main Authors: Gómez, Edwar Jacinto, Santa, Fernando Martínez, Ariza, Holman Montiel
• Format: Journal Article
• Language: English
• Published: Yogyakarta Ahmad Dahlan University 01.12.2019
• Subjects: Algorithms; Buffers; Combinatorial analysis; Counting; Data buses; Data processing; Design; Digital computers; Digital imaging; Electric power systems; Field programmable gate arrays; Finite state machines; Hardware description languages; Image processing; Information processing; Interpolation; Light emitting diodes; Moving images; Object recognition; Personal computers; Power management; Programmable logic devices; Random access memory; Route planning; Transformations (mathematics); Visualization
• ISSN: 1693-6930; 2302-9293; 2302-9293
• DOI: 10.12928/telkomnika.v17i6.12710

Around the transformations [11], extraction of characteristics [12] or any other type of massive matrix operation, object detection and recognition and route planning, Programmable Logic Devices (PLD) have been used, since they require low power and a small amount of space to work [13, 14] in addition to having the ability to perform real-time implementations, working with static and moving images [15], which requires thousands of iterations per second, with maximum use of FPGA resources, both in the combinatorial part (LUT) as in its storage part (memory bank), making efficient the implementations made with this type of devices [16, 17]. The flexibility and performance of hardware development using standard hardware description languages, regardless of the size and architectures of different FPGA's, offers the possibility to test and compare different algorithm resolution methods, which could give different solutions and indicate what family and what architecture would be the most appropriate to use in digital image processing applications [22, 23], using the combination of Soft Cores together with hardware designed to accelerate information processing. The work done begins with the design of a software script on the personal computer, which sends the data of the digital image in binary-ascii format through a serial port emulated towards the FPGA, after that, the programmable logic device processes the information, sends the data to a power system that supports the electrical requirements at the speed required by the array of LEDs and in this way the correct visualization of the information is made. 3.Implementation and Results The first part of the work is shown in the following code, the script reads different formats of images (jpg, png and gif), it will make the conversion to a matrix of valor to create the ROM file, it will be read for the FPGA and put in to LED matrix. imread () /imshow () to verify that it is in full form for processing. im = imread('Mario_8bits.PNG'); figure () imshow(im) In the following code segment, to scale the image the imresize () function is used, which gives us the facility of scaling the value of a square or rectangular matrix to the size to be visualized in the array of LEDs, a bicubic interpolation algorithm was used, a process that guarantees that do not drastically change the information that will be sent to the FPGA. im_small = imresize(im, [32 32], 'cubic'); figure () imshow(im_small) The next code shown that the matrices for the images that are entered were defined for a size of 32x32 being this a square matrix, the selection of the size is based on the space to occupy within the ROM memories that will be of 1024 bits maximum size of each block of memory of a standard FPGA, which has a capacity of 8 times the value of each block generated. im_small_r = im_small(:, im_small_g = im_small(:, im small b = im small(:, The image already scaled is broken down into the 3 matrices of the channels that make up a digital image R (network), G (green) and B (blue), maintaining the intensity characteristics to conform the different color possibilities, in each matrix the values of each pixel have a magnitude between 0 and 255. The input channel of the module (seriai_in) receives the data to work with the waiting of a rising edge for the transmission of the 8 bits. (data_out) is the parallel output of the received data. (read_buffer) in high state of responsible for the transmission of the data to a FIFO memory. (reset_buffer) in active state delete the data saved under the count of 16 data blocks. (en_i6_x_baud) in active state makes the counting of 16 cycles of 8 bits which culminates the storage so that the entire block created in the 16x8 memory will be transmitted. (buffer_data_present) gives an input prompt or that there is information block in the memory. (buffer_fuii or buffer_haif_fuii) indicates in high mode the full state of the memory, indicates how their names say full or half full 16x8/8x8 when it is full memory communicates this state and activates the complete transfer of the memory block wherever your processing is necessary. (cik) system clock for a synchronous multiple system. 3.2.Reception and Storage of Blocks of Information in RAM In the design and implementation of the system it is observed how the CORE of the Uart provided by Xilinx is controlled, by means of a finite state machine, this is in charge of reading the data from the FIFO memory and passing it to the internal RAM memory of the FPGA, in this way it is possible to read blocks of information from the USB-Serial port of the computer to the internal memory, which will then be responsible for displaying the information, as shown in Figure 4.