RETRACTED ARTICLE: High-throughput field-programable gate array implementation of the advanced encryption standard algorithm for automotive security applications

• Published in: Journal of ambient intelligence and humanized computing Vol. 12; no. 7; pp. 7273 - 7279
• Main Authors: Sikka, Prateek, Asati, Abhijit R., Shekhar, Chandra
• Format: Journal Article
• Language: English
• Published: Berlin/Heidelberg Springer Berlin Heidelberg 01.07.2021; Springer Nature B.V
• Subjects: Artificial Intelligence; Computational Intelligence; Engineering; Original Research; Robotics and Automation; User Interfaces and Human Computer Interaction; Field-programable gate array (FPGA); High-level synthesis (HLS); Advanced encryption standard (AES); Register transfer language (RTL); Very large scale integration (VLSI); Vivado high-level synthesis
• ISSN: 1868-5137; 1868-5145
• DOI: 10.1007/s12652-020-02403-2

Connected smart vehicles in automotive industries have increased, resulting in high vehicle-to-vehicle, vehicle-to-infrastructure, and vehicle-to-cloud connectivity. Increased data rates are required to achieve high bandwidth requirements to support such communication networks. Despite having numerous advantages, high connectivity between devices poses threats to vehicle and human security, rendering encryption critical before transmitting data across vehicular networks. Advanced encryption standard (AES) is commonly used for data encryption in automotive microcontrollers. Owing to modern digital design complexities, field-programmable gate arrays (FPGAs) are attracting attention for pre-silicon verification and software development. Owing to their parallel architectures, FPGAs are ideal for prototyping automotive designs running encryption algorithms, like AES at real-time data rates. Moreover, because they are reconfigurable, prototyping results of different implementation choices can be verified at an early stage, thereby helping architects and designers with forthcoming optimal designs. FPGAs also serve as platforms to develop software considerably before silicon arrives, thereby decreasing the time to market. Herein, we propose a high-throughput FPGA implementation of the AES algorithm for automotive microcontrollers using a 128-bit key created via Vivado high-level synthesis (HLS) tool. We use HLS design method based on application-specific bit widths to implement the design on FPGA. The generated design is implemented and verified using Xilinx Kintex 7 and Virtex 6 FPGA; despite identical resource utilization (Look up tables and Flip-Flops), the throughput results are superior to those obtained previously.