Data Flow Algorithms for Processors with Vector Extensions Handling Actors With Internal State
Full use of the parallel computation capabilities of present and expected CPUs and GPUs requires use of vector extensions. Yet many actors in data flow systems for digital signal processing have internal state (or, equivalently, an edge that loops from the actor back to itself) that impose serial de...
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| Published in | Journal of signal processing systems Vol. 87; no. 1; pp. 21 - 31 |
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| Main Authors | , , |
| Format | Journal Article |
| Language | English |
| Published |
New York
Springer US
01.04.2017
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| Subjects | |
| Online Access | Get full text |
| ISSN | 1939-8018 1939-8115 |
| DOI | 10.1007/s11265-015-1045-x |
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| Abstract | Full use of the parallel computation capabilities of present and expected CPUs and GPUs requires use of vector extensions. Yet many actors in data flow systems for digital signal processing have internal state (or, equivalently, an edge that loops from the actor back to itself) that impose serial dependencies between actor invocations that make vectorizing across actor invocations impossible. Ideally, issues of inter-thread coordination required by serial data dependencies should be handled by code written by parallel programming experts that is separate from code specifying signal processing operations. The purpose of this paper is to present one approach for so doing in the case of actors that maintain state. We propose a methodology for using the parallel scan (also known as prefix sum) pattern to create algorithms for multiple simultaneous invocations of such an actor that results in vectorizable code. Two examples of applying this methodology are given: (1) infinite impulse response filters and (2) finite state machines. The correctness and performance of the resulting IIR filters and one class of FSMs are studied. |
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| AbstractList | Full use of the parallel computation capabilities of present and expected CPUs and GPUs requires use of vector extensions. Yet many actors in data flow systems for digital signal processing have internal state (or, equivalently, an edge that loops from the actor back to itself) that impose serial dependencies between actor invocations that make vectorizing across actor invocations impossible. Ideally, issues of inter-thread coordination required by serial data dependencies should be handled by code written by parallel programming experts that is separate from code specifying signal processing operations. The purpose of this paper is to present one approach for so doing in the case of actors that maintain state. We propose a methodology for using the parallel scan (also known as prefix sum) pattern to create algorithms for multiple simultaneous invocations of such an actor that results in vectorizable code. Two examples of applying this methodology are given: (1) infinite impulse response filters and (2) finite state machines. The correctness and performance of the resulting IIR filters and one class of FSMs are studied. |
| Author | Barford, Lee Liu, Yanzhou Bhattacharyya, Shuvra S. |
| Author_xml | – sequence: 1 givenname: Lee surname: Barford fullname: Barford, Lee email: lee.barford@keysight.com organization: Keysight Laboratories, Keysight Technologies, Inc – sequence: 2 givenname: Shuvra S. surname: Bhattacharyya fullname: Bhattacharyya, Shuvra S. organization: University of Maryland, Tampere University of Technology – sequence: 3 givenname: Yanzhou surname: Liu fullname: Liu, Yanzhou organization: University of Maryland |
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| Cites_doi | 10.1109/I2MTC.2012.6229207 10.1109/PACT.2011.68 10.1145/1866739.1866760 10.1109/31.76483 10.1016/j.parco.2011.09.001 10.1145/1375527.1375559 10.1109/32.99191 10.1109/MAHC.2010.28 10.1109/TC.1987.5009446 10.1109/IPDPSW.2013.207 10.1109/ISPDC.2012.17 10.1109/I2MTC.2014.6860775 10.1109/MC.1980.1653418 10.1109/IPDPSW.2013.141 10.1109/TIM.2010.2090055 10.1090/S0002-9947-1965-0188316-1 10.1145/1365490.1365500 10.1109/ARITH.2013.24 10.1145/258492.258518 10.1007/978-3-662-44199-2_13 10.1016/S0019-9958(78)90320-0 10.1145/322217.322232 10.1109/SC.2006.31 10.1007/BF02406474 10.1109/12.42122 10.1109/ASAP.1993.397152 |
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| Keywords | Data flow computing Vector processors Parallel algorithms Graphics processing units Digital signal processing |
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Pearson Education. – reference: ParhiKKHigh-Level algorithm and architecture transformations for DSP synthesisJournal of VLSI Signal Processing199591210.1007/BF02406474 – reference: AsanovicKBodikRCatanzaroBCGebisJJHusbandsPKeutzerKPattersonDAPlishkerWLShalfJWilliamsSWThe landscape of parallel computing research: A view from Berkeley. Tech. rep., Technical Report UCB/EECS-2006-183, EECS Department2006BerkeleyUniversity of California – reference: Mitra, G., Johnston, B., Rendell, A.P., McCreath, E., & Zhou, J. (2013). Use of SIMD vector operations to accelerate application code performance on low-powered ARM and Intel platforms. In 2013 IEEE 27th International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), (pp. 1107–1116). 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| Snippet | Full use of the parallel computation capabilities of present and expected CPUs and GPUs requires use of vector extensions. Yet many actors in data flow systems... |
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| SubjectTerms | Circuits and Systems Computer Imaging Electrical Engineering Engineering Image Processing and Computer Vision Pattern Recognition Pattern Recognition and Graphics Signal,Image and Speech Processing Vision |
| Subtitle | Handling Actors With Internal State |
| Title | Data Flow Algorithms for Processors with Vector Extensions |
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