Fast Sign Detection Algorithm for the RNS Moduli Set \-1, 2^-1, 2

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 23; no. 2; pp. 379 - 383
• Main Authors: Minghe Xu, Zhenpeng Bian, Ruohe Yao
• Format: Journal Article
• Language: English
• Published: IEEE 01.02.2015
• Subjects: Adders; Computer arithmetic; Delays; Detection algorithms; Hardware; Optimization; residue number system (RNS); restricted moduli set; sign detection; Very large scale integration; residue number system (RNS); sign detection; restricted moduli set; Computer arithmetic
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2014.2308014

This brief presents a fast sign detection algorithm for the residue number system moduli set {2 n+1 - 1, 2 n - 1, 2 n }. First, a sign detection algorithm for the restricted moduli set is described. The new algorithm allows for parallel implementation and consists exclusively of modulo 2 n additions. Then, a sign detection unit for the moduli set {2 n+1 - 1, 2 n - 1, 2 n } is proposed based on the new sign detection algorithm. The unit can be implemented using one carry save adder, one comparator and one prefix adder. The experimental results demonstrate that the proposed circuit unit offers 63.8%, 44.9%, and 67.6% savings on average in area, delay and power, respectively, compared with a unit based on one of the best sign detection algorithms.