Clock gating for power optimization in ASIC design cycle theory & practice - S, Jairam; Rao, Madhusudan; Srinivas, Jithendra; Vishwanath, Parimala; H, Udayakumar; Rao, Jagdish (Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08), 2008)
Keywords: Application specific integrated circuits; ASIC; Character generation; Clocks; Design methodology; Design optimization; Dynamic voltage scaling; Electronic design automation and methodology; Hardware -- Electronic design automation -- Hardware description languages and compilation; Hardware -- Electronic design automation -- Logic synthesis -- Circuit optimization; History; Logic; low power; optimization; RTL; SoC; Technological innovation; low power; ASIC; RTL; optimization; SoC