The designer's guide to VHDL
Since the publication of the first edition of The Designer's Guide to VHDL in 1996, digital electronic systems have increased exponentially in their complexity, product lifetimes have dramatically shrunk, and reliability requirements have shot through the roof. As a result more and more designe...
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| Main Author | |
|---|---|
| Format | eBook Book |
| Language | English |
| Published |
San Francisco, Calif
Morgan Kaufmann
2002
Elsevier Science & Technology |
| Edition | 2 |
| Series | Systems on Silicon |
| Subjects | |
| Online Access | Get full text |
| ISBN | 1558606742 9781558606746 |
Cover
Table of Contents:
- Front Cover -- The Designer's Guide to VHDL -- Copyright Page -- Contents -- Foreword -- Foreword to the First Edition -- Preface -- Chapter 1. Fundamental Concepts -- Modeling Digital Systems -- Domains and Levels of Modeling -- Modeling Languages -- VHDL Modeling Concepts -- Learning a New Language: Lexical Elements and Syntax -- Exercises -- Chapter 2. Scalar Data Types and Operations -- Constants and Variables -- Scalar Types -- Type Classification -- Attributes of Scalar Types -- Expressions and Operators -- Exercises -- Chapter 3. Sequential Statements -- If Statements -- Case Statements -- Null Statements -- Loop Statements -- Assertion and Report Statements -- Exercises -- Chapter 4. Composite Data Types and Operations -- Arrays -- Unconstrained Array Types -- Array Operations and Referencing -- Records -- Exercises -- Chapter 5. Basic Modeling Constructs -- Entity Declarations -- Architecture Bodies -- Behavioral Descriptions -- Structural Descriptions -- Design Processing -- Exercises -- Chapter 6. Case Study: A Pipelined Multiplier Accumulator -- Algorithm Outline -- A Behavioral Model -- A Register-Transfer-Level Model -- Exercises -- Chapter 7. Subprograms -- Procedures -- Procedure Parameters -- Concurrent Procedure Call Statements -- Functions -- Overloading -- Visibility of Declarations -- Exercises -- Chapter 8. Packages and Use Clauses -- Package Declarations -- Package Bodies -- Use Clauses -- The Predefined Package Standard -- IEEE Standard Packages -- Exercises -- Chapter 9. Aliases -- Aliases for Data Objects -- Aliases for Non-Data Items -- Exercises -- Chapter 10. Case Study: A Bit-Vector Arithmetic Package -- The Package Interface -- The Package Body -- An ALU Using the Arithmetic Package -- Exercises -- Chapter 11. Resolved Signals -- Basic Resolved Signals -- IEEE Std_Logic_1164 Resolved Subtypes
- Resolved Signals and Ports -- Resolved Signal Parameters -- Exercises -- Chapter 12. Generic Constants -- Parameterizing Behavior -- Parameterizing Structure -- Exercises -- Chapter 13. Generic Constants Components and Configurations -- Components -- Configuring Component Instances -- Configuration Specifications -- Exercises -- Chapter 14. Generate Statements -- Generating Iterative Structures -- Conditionally Generating Structures -- Configuration of Generate Statements -- Exercises -- Chapter 15. Case Study: The DLX Computer System -- Overview of the DLX CPU -- A Behavioral Model -- Testing the Behavioral Model -- A Register-Transfer-Level Model -- Testing the Register-Transfer-Level Model -- Exercises -- Chapter 16. Guards and Blocks -- Guarded Signals and Disconnection -- Blocks and Guarded Signal Assignment -- Using Blocks for Structural Modularity -- Exercises -- Chapter 17. Access Types and Abstract Data Types -- Access Types -- Linked Data Structures -- Abstract Data Types Using Packages -- Exercises -- Chapter 18. Files and Input/Output -- Files -- The Package Textio -- Exercises -- Chapter 19. Case Study: Queuing Networks -- Queuing Network Concepts -- Queuing Network Modules -- A Queuing Network for a Disk System -- Exercises -- Chapter 20. Attributes and Groups -- Predefined Attributes -- User-Defined Attributes -- Groups -- Exercises -- Chapter 21. Miscellaneous Topics -- Buffer and Linkage Ports -- Conversion Functions in Association Lists -- Postponed Processes -- Shared Variables -- Exercises -- Chapter A. Synthesis -- Use of Data Types -- Interpretation of Standard Logic Values -- Modeling Combinatorial Logic -- Modeling Sequential Logic -- VHDL Modeling Restrictions -- Chapter B. The Predefined Package Standard -- Chapter C. IEEE Standard Packages -- Std_Logic_1164 Multivalue Logic System1
- Standard 1076.3 VHDL Synthesis Packages2 -- Standard 1076.2 VHDL Mathematical Packages3 -- Chapter D. Related Standards -- IEEE VHDL Standards -- Other Design Automation Standards -- Chapter E. VHDL Syntax -- Design File -- Library Unit Declarations -- Declarations and Specifications -- Type Definitions -- Concurrent Statements -- Sequential Statements -- Interfaces and Associations -- Expressions -- Chapter F. Differences among VHDL-87, VHDL-93 and VHDL-2001 -- Lexical Differences -- Syntactic Differences -- Semantic Differences -- Differences in the Standard Environment -- VHDL-93 Facilities Not in VHDL-87 -- VHDL-2001 Facilities Not in VHDL-87 or VHDL-93 -- Features under Consideration for Removal -- Chapter G. Answers to Exercises -- Chapter H. Software Guide -- Software Overview -- Installation -- Example VHDL Code -- Exploration/VHDL Quick Start Guide -- Example -- References -- Index