APA (7th ed.) Citation

Gerkšič, S., & Pregelj, B. (2021, March 19). Finite-word-length FPGA implementation of model predictive control for ITER resistive wall mode control. arXiv.org. https://doi.org/10.48550/arxiv.2103.10146

Chicago Style (17th ed.) Citation

Gerkšič, Samo, and Boštjan Pregelj. "Finite-word-length FPGA Implementation of Model Predictive Control for ITER Resistive Wall Mode Control." ArXiv.org 19 Mar. 2021. https://doi.org/10.48550/arxiv.2103.10146.

MLA (9th ed.) Citation

Gerkšič, Samo, and Boštjan Pregelj. "Finite-word-length FPGA Implementation of Model Predictive Control for ITER Resistive Wall Mode Control." ArXiv.org, 19 Mar. 2021, https://doi.org/10.48550/arxiv.2103.10146.