DSP architecture design essentials

This book addresses the gap between DSP algorithm design and implementation, using an approach to DSP architecture design that merges algorithm and system specifications with the intrinsic computational capability of the underlying technology.

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Bibliographic Details
Main Authors Marković, Dejan, Brodersen, Robert W.
Format eBook Book
LanguageEnglish
Published New York Springer 2012
Springer US
Edition1
SeriesElectrical Engineering Essentials
Subjects
Circuits and Systems
Design and construction
Digital techniques
Electrical Engineering
Engineering
Microprocessors
Processor Architectures
Programming
Signal processing
Signal processing > Digital techniques > Data processing
Signal, Image and Speech Processing
Software architecture
Online AccessGet full text
ISBN9781441996596
1441996591
1441996605
9781441996602
DOI10.1007/978-1-4419-9660-2

Cover

Table of Contents:
  • Slide 4.10 -- Slide 4.11 -- Slide 4.12 -- Slide 4.13 -- Slide 4.14 -- Slide 4.15 -- Slide 4.16 -- Slide 4.17 -- Slide 4.18 -- Slide 4.19 -- Slide 4.20 -- Slide 4.21 -- References -- Part II DSP Operations and Their Architecture -- Chapter 5 Arithmetic for DSP -- Slide 5.1 -- Slide 5.2 -- Slide 5.3 -- Slide 5.4 -- Slide 5.5 -- Slide 5.6 -- Slide 5.7 -- Slide 5.8 -- Slide 5.9 -- Slide 5.10 -- Slide 5.11 -- Slide 5.12 -- Slide 5.13 -- Slide 5.14 -- Slide 5.15 -- Slide 5.16 -- Slide 5.17 -- Slide 5.18 -- Slide 5.19 -- Slide 5.20 -- Slide 5.21 -- Slide 5.22 -- Slide 5.23 -- Slide 5.24 -- Slide 5.25 -- Slide 5.26 -- Slide 5.27 -- Slide 5.28 -- Slide 5.29 -- Slide 5.30 -- Slide 5.31 -- Slide 5.32 -- Slide 5.33 -- Slide 5.34 -- Slide 5.35 -- Slide 5.36 -- References -- Additional References -- Chapter 6 CORDIC, Divider, Square Root -- Slide 6.1 -- Slide 6.2 -- Slide 6.3 -- Slide 6.4 -- Slide 6.5 -- Slide 6.6 -- Slide 6.7 -- Slide 6.8 -- Slide 6.9 -- Slide 6.10 -- Slide 6.11 -- Slide 6.12 -- Slide 6.13 -- Slide 6.14 -- Slide 6.15 -- Slide 6.16 -- Slide 6.17 -- Slide 6.18 -- Slide 6.19 -- Slide 6.20 -- Slide 6.21 -- Slide 6.22 -- Slide 6.23 -- Slide 6.24 -- Slide 6.25 -- Slide 6.26 -- Slide 6.27 -- Slide 6.28 -- Slide 6.29 -- Slide 6.30 -- Slide 6.31 -- Slide 6.32 -- Slide 6.33 -- Slide 6.34 -- Slide 6.35 -- Slide 6.36 -- Slide 6.37 -- Slide 6.38 -- Slide 6.39 -- References -- Additional References -- Chapter 7 Digital Filters -- Slide 7.1 -- Slide 7.2 -- Slide 7.3 -- Slide 7.4 -- Slide 7.5 -- Slide 7.6 -- Slide 7.7 -- Slide 7.8 -- Slide 7.9 -- Slide 7.10 -- Slide 7.11 -- Slide 7.12 -- Slide 7.13 -- Slide 7.14 -- Slide 7.15 -- Slide 7.16 -- Slide 7.17 -- Slide 7.18 -- Slide 7.19 -- Slide 7.20 -- Slide 7.21 -- Slide 7.22 -- Slide 7.23 -- Slide 7.24 -- Slide 7.25 -- Slide 7.26 -- Slide 7.27 -- Slide 7.28 -- Slide 7.29 -- Slide 7.30 -- Slide 7.31 -- Slide 7.32
  • Slide 10.25 -- Slide 10.26 -- Slide 10.27 -- References -- Chapter 11 Architectural Optimization -- Slide 11.1 -- Slide 11.2 -- Slide 11.3 -- Slide 11.4 -- Slide 11.5 -- Slide 11.6 -- Slide 11.7 -- Slide 11.8 -- Slide 11.9 -- Slide 11.10 -- Slide 11.11 -- Slide 11.12 -- Slide 11.13 -- Slide 11.14 -- Slide 11.15 -- Slide 11.16 -- Slide 11.17 -- Slide 11.18 -- Slide 11.19 -- Slide 11.20 -- Slide 11.21 -- Slide 11.22 -- Slide 11.23 -- Slide 11.24 -- Slide 11.25 -- Slide 11.26 -- Slide 11.27 -- Slide 11.28 -- Slide 11.29 -- Slide 11.30 -- Slide 11.31 -- Slide 11.32 -- Slide 11.33 -- Slide 11.34 -- Slide 11.35 -- Slide 11.36 -- Slide 11.37 -- Slide 11.38 -- Slide 11.39 -- Slide 11.40 -- Slide 11.41 -- Slide 11.42 -- References -- Chapter 12 Simulink-Hardware Flow -- Slide 12.1 -- Slide 12.2 -- Slide 12.3 -- Slide 12.4 -- Slide 12.5 -- Slide 12.6 -- Slide 12.7 -- Slide 12.8 -- Slide 12.9 -- Slide 12.10 -- Slide 12.11 -- Slide 12.12 -- Slide 12.13 -- Slide 12.14 -- Slide 12.15 -- Slide 12.16 -- Slide 12.17 -- Slide 12.18 -- Slide 12.19 -- Slide 12.20 -- Slide 12.21 -- Slide 12.22 -- Slide 12.23 -- Slide 12.24 -- Slide 12.25 -- Slide 12.26 -- Slide 12.27 -- Slide 12.28 -- Slide 12.29 -- Slide 12.30 -- Slide 12.31 -- Slide 12.32 -- Slide 12.33 -- Slide 12.34 -- Slide 12.35 -- Slide 12.36 -- Slide 12.37 -- Slide 12.38 -- Slide 12.39 -- Slide 12.40 -- Slide 12.41 -- Slide 12.42 -- Slide 12.43 -- Slide 12.44 -- Slide 12.45 -- Slide 12.46 -- Slide 12.47 -- Slide 12.48 -- Slide 12.49 -- References -- Part IV Design Examples: GHz to kHz -- Chapter 13 Multi-GHz Radio DSP -- Slide 13.1 -- Slide 13.2 -- Slide 13.3 -- Slide 13.4 -- Slide 13.5 -- Slide 13.6 -- Slide 13.7 -- Slide 13.8 -- Slide 13.9 -- Slide 13.10 -- Slide 13.11 -- Slide 13.12 -- Slide 13.13 -- Slide 13.14 -- Slide 13.15 -- Slide 13.16 -- Slide 13.17 -- Slide 13.18 -- Slide 13.19 -- Slide 13.20
  • Slide 13.21 -- Slide 13.22 -- Slide 13.23 -- Slide 13.24 -- Slide 13.25 -- Slide 13.26 -- Slide 13.27 -- Slide 13.28 -- Slide 13.29 -- Slide 13.30 -- Slide 13.31 -- Slide 13.32 -- Slide 13.33 -- Slide 13.34 -- Slide 13.35 -- Slide 13.36 -- Slide 13.37 -- Slide 13.38 -- References -- Chapter 14 MHz-rate Multi-Antenna Decoders: Dedicated SVD Chip Example -- Slide 14.1 -- Slide 14.2 -- Slide 14.3 -- Slide 14.4 -- Slide 14.5 -- Slide 14.6 -- Slide 14.7 -- Slide 14.8 -- Slide 14.9 -- Slide 14.10 -- Slide 14.11 -- Slide 14.12 -- Slide 14.13 -- Slide 14.14 -- Slide 14.15 -- Slide 14.16 -- Slide 14.17 -- Slide 14.18 -- Slide 14.19 -- Slide 14.20 -- Slide 14.21 -- Slide 14.22 -- Slide 14.23 -- Slide 14.24 -- Slide 14.25 -- Slide 14.26 -- Slide 14.27 -- Slide 14.28 -- Slide 14.29 -- Slide 14.30 -- Slide 14.31 -- Slide 14.32 -- References -- Additional References -- Chapter 15 MHz-rate Multi-Antenna Decoders: Flexible Sphere Decoder Chip Examples -- Slide 15.1 -- Slide 15.2 -- Slide 15.3 -- Slide 15.4 -- Slide 15.5 -- Slide 15.6 -- Slide 15.7 -- Slide 15.8 -- Slide 15.9 -- Slide 15.10 -- Slide 15.11 -- Slide 15.12 -- Slide 15.13 -- Slide 15.14 -- Slide 15.15 -- Slide 15.16 -- Slide 15.17 -- Slide 15.18 -- Slide 15.19 -- Slide 15.20 -- Slide 15.21 -- Slide 15.22 -- Slide 15.23 -- Slide 15.24 -- Slide 15.25 -- Slide 15.26 -- Slide 15.27 -- Slide 15.28 -- Slide 15.29 -- Slide 15.30 -- Slide 15.31 -- Slide 15.32 -- Slide 15.33 -- Slide 15.34 -- Slide 15.35 -- Slide 15.36 -- Slide 15.37 -- Slide 15.38 -- Slide 15.39 -- Slide 15.40 -- Slide 15.41 -- Slide 15.42 -- Slide 15.43 -- Slide 15.44 -- Slide 15.45 -- Slide 15.46 -- Slide 15.47 -- Slide 15.48 -- References -- Chapter 16 kHz-Rate Neural Processors -- Slide 16.1 -- Slide 16.2 -- Slide 16.3 -- Slide 16.4 -- Slide 16.5 -- Slide 16.6 -- Slide 16.7 -- Slide 16.8 -- Slide 16.9 -- Slide 16.10 -- Slide 16.11
  • Intro -- DSP Architecture Design Essentials -- Contents -- Preface -- Slide P.1 -- Slide P.2 -- Slide P.3 -- Slide P.4 -- Slide P.5 -- Slide P.6 -- Slide P.7 -- Slide P.8 -- Slide P.9 -- Slide P.10 -- Slide P.11 -- Slide P.12 -- Part I Technology Metrics -- Chapter 1 Energy and Delay Models -- Slide 1.1 -- Slide 1.2 -- Slide 1.3 -- Slide 1.4 -- Slide 1.5 -- Slide 1.6 -- Slide 1.7 -- Slide 1.8 -- Slide 1.9 -- Slide 1.10 -- Slide 1.11 -- Slide 1.12 -- Slide 1.13 -- Slide 1.14 -- Slide 1.15 -- Slide 1.16 -- Slide 1.17 -- Slide 1.18 -- Slide 1.19 -- Slide 1.20 -- Slide 1.21 -- Slide 1.22 -- Slide 1.23 -- Slide 1.24 -- Slide 1.25 -- Slide 1.26 -- Slide 1.27 -- Slide 1.28 -- References -- Additional References -- Chapter 2 Circuit Optimization -- Slide 2.1 -- Slide 2.2 -- Slide 2.3 -- Slide 2.4 -- Slide 2.5 -- Slide 2.6 -- Slide 2.7 -- Slide 2.8 -- Slide 2.9 -- Slide 2.10 -- Slide 2.11 -- Slide 2.12 -- Slide 2.13 -- Slide 2.14 -- Slide 2.15 -- Slide 2.16 -- Slide 2.17 -- Slide 2.18 -- Slide 2.19 -- Slide 2.20 -- Slide 2.21 -- Slide 2.22 -- Slide 2.23 -- Slide 2.24 -- Slide 2.25 -- Slide 2.26 -- Slide 2.27 -- Slide 2.28 -- Slide 2.29 -- Slide 2.30 -- References -- Additional References -- Chapter 3 Architectural Techniques -- Slide 3.1 -- Slide 3.2 -- Slide 3.3 -- Slide 3.4 -- Slide 3.5 -- Slide 3.6 -- Slide 3.7 -- Slide 3.8 -- Slide 3.9 -- Slide 3.10 -- Slide 3.11 -- Slide 3.12 -- Slide 3.13 -- Slide 3.14 -- Slide 3.15 -- Slide 3.16 -- Slide 3.17 -- Slide 3.18 -- Slide 3.19 -- Slide 3.20 -- Slide 3.21 -- Slide 3.22 -- Slide 3.23 -- Slide 3.24 -- Slide 3.25 -- Slide 3.26 -- Slide 3.27 -- Slide 3.28 -- Slide 3.29 -- Slide 3.30 -- Slide 3.31 -- Slide 3.32 -- References -- Additional References -- Chapter 4 Architecture Flexibility -- Slide 4.1 -- Slide 4.2 -- Slide 4.3 -- Slide 4.4 -- Slide 4.5 -- Slide 4.6 -- Slide 4.7 -- Slide 4.8 -- Slide 4.9
  • Slide 7.33 -- Slide 7.34 -- Slide 7.35 -- Slide 7.36 -- Slide 7.37 -- Slide 7.38 -- Slide 7.39 -- Slide 7.40 -- Slide 7.41 -- Slide 7.42 -- Slide 7.43 -- Slide 7.44 -- Slide 7.45 -- Slide 7.46 -- Slide 7.47 -- Slide 7.48 -- Slide 7.49 -- Slide 7.50 -- Slide 7.51 -- Slide 7.52 -- Slide 7.53 -- Slide 7.54 -- Slide 7.55 -- Slide 7.56 -- Slide 7.57 -- Slide 7.58 -- Slide 7.59 -- References -- Additional References -- Chapter 8 Time-Frequency Analysis: FFT and Wavelets -- Slide 8.1 -- Slide 8.2 -- Slide 8.3 -- Slide 8.4 -- Slide 8.5 -- Slide 8.6 -- Slide 8.7 -- Slide 8.8 -- Slide 8.9 -- Slide 8.10 -- Slide 8.11 -- Slide 8.12 -- Slide 8.13 -- Slide 8.14 -- Slide 8.15 -- Slide 8.16 -- Slide 8.17 -- Slide 8.18 -- Slide 8.19 -- Slide 8.20 -- Slide 8.21 -- Slide 8.22 -- Slide 8.23 -- Slide 8.24 -- Slide 8.25 -- Slide 8.26 -- Slide 8.27 -- Slide 8.28 -- Slide 8.29 -- Slide 8.30 -- Slide 8.31 -- Slide 8.32 -- Slide 8.33 -- Slide 8.34 -- Slide 8.35 -- Slide 8.36 -- Slide 8.37 -- Slide 8.38 -- Slide 8.39 -- Slide 8.40 -- Slide 8.41 -- Slide 8.42 -- Slide 8.43 -- Slide 8.44 -- Slide 8.45 -- Slide 8.46 -- Slide 8.47 -- Slide 8.48 -- Slide 8.49 -- References -- Additional References -- Part III Architecture Modeling and Optimized Implementation -- Chapter 9 Data-Flow Graph Model -- Slide 9.1 -- Slide 9.2 -- Slide 9.3 -- Slide 9.4 -- Slide 9.5 -- Slide 9.6 -- Slide 9.7 -- Slide 9.8 -- Slide 9.9 -- Slide 9.10 -- Slide 9.11 -- Slide 9.12 -- Slide 9.13 -- Slide 9.14 -- References -- Chapter 10 Wordlength Optimization -- Slide 10.1 -- Slide 10.2 -- Slide 10.3 -- Slide 10.4 -- Slide 10.5 -- Slide 10.6 -- Slide 10.7 -- Slide 10.8 -- Slide 10.9 -- Slide 10.10 -- Slide 10.11 -- Slide 10.12 -- Slide 10.13 -- Slide 10.14 -- Slide 10.15 -- Slide 10.16 -- Slide 10.17 -- Slide 10.18 -- Slide 10.19 -- Slide 10.20 -- Slide 10.21 -- Slide 10.22 -- Slide 10.23 -- Slide 10.24
  • Slide 16.12