Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations

• Published in: VLSI Design Vol. 2010; no. 2010; pp. 33 - 45
• Main Authors: Yelamarthi, Kumar, Chen, Chien-In Henry
• Format: Journal Article
• Language: English
• Published: Cairo, Egypt Hindawi Limiteds 01.01.2010; Hindawi Puplishing Corporation; Hindawi Publishing Corporation; Hindawi Limited
• Subjects: Computer engineering; Design; Logic; Methods; Microprocessors; Studies
• ISSN: 1065-514X; 1563-5171; 1026-7123; 1563-5171
• DOI: 10.1155/2010/230783

The complexity of timing optimization of high-performance circuits has been increasing rapidly in proportion to the shrinking CMOS device size and rising magnitude of process variations. Addressing these significant challenges, this paper presents a timing optimization algorithm for CMOS dynamic logic and a Path Oriented IN Time (POINT) optimization flow for mixed-static-dynamic CMOS logic, where a design is partitioned into static and dynamic circuits. Implemented on a 64-b adder and International Symposium on Circuits and Systems (ISCAS) benchmark circuits, the POINT optimization algorithm has shown an average improvement in delay by 38% and delay uncertainty from process variations by 35% in comparison with a state-of-the-art commercial optimization tool.