Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations
The complexity of timing optimization of high-performance circuits has been increasing rapidly in proportion to the shrinking CMOS device size and rising magnitude of process variations. Addressing these significant challenges, this paper presents a timing optimization algorithm for CMOS dynamic log...
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| Published in | VLSI Design Vol. 2010; no. 2010; pp. 33 - 45 |
|---|---|
| Main Authors | , |
| Format | Journal Article |
| Language | English |
| Published |
Cairo, Egypt
Hindawi Limiteds
01.01.2010
Hindawi Puplishing Corporation Hindawi Publishing Corporation Hindawi Limited |
| Subjects | |
| Online Access | Get full text |
| ISSN | 1065-514X 1563-5171 1026-7123 1563-5171 |
| DOI | 10.1155/2010/230783 |
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| Abstract | The complexity of timing optimization of high-performance circuits has been increasing rapidly in proportion to the shrinking CMOS device size and rising magnitude of process variations. Addressing these significant challenges, this paper presents a timing optimization algorithm for CMOS dynamic logic and a Path Oriented IN Time (POINT) optimization flow for mixed-static-dynamic CMOS logic, where a design is partitioned into static and dynamic circuits. Implemented on a 64-b adder and International Symposium on Circuits and Systems (ISCAS) benchmark circuits, the POINT optimization algorithm has shown an average improvement in delay by 38% and delay uncertainty from process variations by 35% in comparison with a state-of-the-art commercial optimization tool. |
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| AbstractList | The complexity of timing optimization of high-performance circuits has been increasing rapidly in proportion to the shrinking CMOS device size and rising magnitude of process variations. Addressing these significant challenges, this paper presents a timing optimization algorithm for CMOS dynamic logic and a Path Oriented IN Time (POINT) optimization flow for mixed-static-dynamic CMOS logic, where a design is partitioned into static and dynamic circuits. Implemented on a 64-b adder and International Symposium on Circuits and Systems (ISCAS) benchmark circuits, the POINT optimization algorithm has shown an average improvement in delay by 38% and delay uncertainty from process variations by 35% in comparison with a state-of-the-art commercial optimization tool. |
| Author | Chen, Chien-In Henry Yelamarthi, Kumar |
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| Cites_doi | 10.1109/43.998628 10.1109/4.982424 10.1109/43.892856 10.1109/4.668981 10.1109/54.785838 10.1109/JSSC.2005.848021 10.1109/TVLSI.2006.878226 10.1147/rd.446.0799 10.1109/82.809537 |
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| Contributor | Chen, Chien-In Henry |
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| Copyright | Copyright © 2010 Copyright © 2010 Kumar Yelamarthi et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. |
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| References_xml | – volume: 14 start-page: 646 issue: 6 year: 2006 end-page: 649 ident: 23 article-title: A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits – reference: McGuinnessP.Patrick.Mcguinness@freescale.comVariations, margins, and statisticsProceedings of the International Symposium on Physical DesignApril 2008Portland, Ore, USA60672-s2.0-3474886492310.1145/1353629.1353643 – reference: BurnettD.EringtonK.SubramanianC.BakerK.Implications of fundamental threshold voltage variations for high-density SRAM and logic circuitsProceedings of the Symposium on VLSI TechnologyJune 1994Honolulu, Hawaii, USA15162-s2.0-0028571338 – reference: BorkarS.KarnikT.NarendraS.TschanzJ.KeshavarziA.DeV.Parameter variations and impact on circuits and microarchitectureProceedings of Design Automation Conference20033383422-s2.0-0041633858 – reference: TakeuchiK.TatsumiT.FurukawaA.Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuationProceedings of the IEEE Electron Devices Meeting (IDEM '97)December 1997Washington, DC, USA84184410.1109/IEDM.1997.6505122-s2.0-0031380264 – reference: ZhangL.Statistical timing analysis for digital circuit design, Ph.D. dissertationDecember 2005 – reference: TschanzJ.BowmanK.DeV.Variation-tolerant circuits: circuit solutions and techniquesProceedings of Design Automation Conference20057627632-s2.0-27944486592 – reference: WesteN.HarrisD.CMOS VLSI Design: A Circuits and Systems Perspective20043rdBoston, Mass, USAAddison Wesley – reference: SamaanS. B.The impact of device parameter variations on the frequency and performance of VLSI chipsProceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD '04)20043433462-s2.0-16244383198 – reference: WolfW.Modern VLSI Design: IP-Based Design20084thUpper Saddle River, NJ, USAPrentice Hall – reference: Synopsys PrimeTimehttp://www.synopsys.com/ – reference: Cadence Encounterhttp://www.cadence.com/ – reference: SchefferL.The Count of Monte CarloProceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU '04)February 2004 – reference: LasbouyguesB.WilsonR.AzemardN.MaurineP.Timing analysis in presence of supply voltage and temperature variationsProceedings of the International Symposium on Physical Design200610162-s2.0-33745933647 – reference: PuriR.Design issues in mixed static-dynamic circuit implementationProceedings of International Conference on Computer Design1998270275 – reference: SutherlandI.SproullB.HarrisD.Logical Effort: Designing Fast CMOS Circuits1999San Francisco, Calif, USAMorgan Kaufmann – reference: WangW.YangS.BhardwajS.The impact of NBTI on the performance of combinational and sequential circuitsProceedings of the 44th Annual Design Automation Conference200736436910.1109/DAC.2007.3751882-s2.0-34547342641 – reference: OrshanskyM.Increasing Circuit Performance through Statistical Design Techniques2003Dordrecht, The NetherlandsKluwer Academic PublishersClosing the Gap between ASIC & Custom – reference: ZuchowskiP. S.HabitzP. A.HayesJ. D.OppoldJ. H.Process and environmental variation impacts on ASIC timingProceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD '04)November 20043363422-s2.0-16244389977 – reference: ConnA. R.ElfadelI. M.MolzenW. W.Jr.Gradient-based optimization of custom circuits using a static-timing formulationProceedings of Design Automation ConferenceJune 19994524592-s2.0-0032667128 – volume: 46 start-page: 1512 issue: 12 year: 1999 end-page: 1515 ident: 25 article-title: Performing arithmetic functions with the Chinese abacus approach – volume: 40 start-page: 1212 issue: 6 year: 2005 end-page: 1224 ident: 27 article-title: Device mismatch and tradeoffs in the design of analog circuits – reference: JungS.-O.KimK.-W.KangS.-M.Transistor sizing for reliable domino logic design in dual threshold voltage technologiesProceedings of the 11th Great Lakes Symposium on VLSI (GLSVLSI '01)March 2001West Lafayette, Ind, USA1331382-s2.0-0034996130 – reference: FuB.YuQ.AmpaduP.Energy-delay minimization in nanoscale domino logicProceedings of the 16th ACM Great Lakes Symposium on VLSI (GLSVLSI '06)April 2006Philadelphia, Pa, USA3163192-s2.0-33750903324 – reference: Synopsys Design Compilerhttp://www.synopsys.com/ – volume: 33 start-page: 676 issue: 5 year: 1998 end-page: 685 ident: 2 article-title: High-performance microprocessor design – volume: 21 start-page: 568 issue: 5 year: 2002 end-page: 581 ident: 11 article-title: Fast and exact transistor sizing based on iterative relaxation – volume: 16 start-page: 72 issue: 3 year: 1999 end-page: 80 ident: 34 article-title: Unveiling the ISCAS-85 benchmarks: a case study in reverse engineering – volume: 19 start-page: 1322 issue: 11 year: 2000 end-page: 1336 ident: 3 article-title: Timing-driven partitioning and timing optimization of mixed static-domino implementations – reference: LuoZ.General transistor-level methodology on VLSI low-power designProceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI '06)April 2006Philadelphia, Pa, USA1151182-s2.0-33750899846 – reference: YelamarthiK.ChenC.-I. H.A path oriented in time optimization flow for mixed-static-dynamic CMOS logicProceedings of the 51st Midwest Symposium on Circuits and SystemsAugust 2008Knoxville, Tenn, USA45445710.1109/MWSCAS.2008.46168342-s2.0-54249098742 – reference: FishburnJ. P.DunlopA. E.TILOS: a posynomial programming approach to transistor sizingProceedings of IEEE International Conference on Computer Aided Design (CCAD '85)1985Santa Clara, Calif, USA3263282-s2.0-0022231945 – reference: BorahM.OwensR. M.IrwinM. J.Transistor sizing for minimizing power consumption of CMOS circuits under delay constraintProceedings of the International Symposium on Low Power DesignApril 1995Dana Point, Calif, USA1671722-s2.0-0029178885 – volume: 44 start-page: 799 issue: 6 year: 2000 end-page: 822 ident: 1 article-title: Custom circuit design as a driver of microprocessor performance – volume: 37 start-page: 183 issue: 2 year: 2002 end-page: 190 ident: 18 article-title: Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration – ident: 11 doi: 10.1109/43.998628 – ident: 18 doi: 10.1109/4.982424 – ident: 3 doi: 10.1109/43.892856 – volume: 33 start-page: 676 issue: 5 year: 1998 ident: 2 publication-title: IEEE Journal of Solid-State Circuits doi: 10.1109/4.668981 – year: 2004 ident: 17 – ident: 34 doi: 10.1109/54.785838 – year: 2003 ident: 19 – year: 2008 ident: 28 – ident: 26 doi: 10.1109/JSSC.2005.848021 – year: 1999 ident: 16 – ident: 23 doi: 10.1109/TVLSI.2006.878226 – volume: 44 start-page: 799 issue: 6 year: 2000 ident: 1 publication-title: IBM Journal of Research and Development doi: 10.1147/rd.446.0799 – ident: 25 doi: 10.1109/82.809537 |
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| Title | Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations |
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