APA (7th ed.) Citation

Yelamarthi, K., & Chen, C. H. (2010). Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations. VLSI Design, 2010(2010), 33-45. https://doi.org/10.1155/2010/230783

Chicago Style (17th ed.) Citation

Yelamarthi, Kumar, and Chien-In Henry Chen. "Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations." VLSI Design 2010, no. 2010 (2010): 33-45. https://doi.org/10.1155/2010/230783.

MLA (9th ed.) Citation

Yelamarthi, Kumar, and Chien-In Henry Chen. "Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations." VLSI Design, vol. 2010, no. 2010, 2010, pp. 33-45, https://doi.org/10.1155/2010/230783.