A methodology to improve timing yield in the presence of process variations - Raj, Sreeja; Vrudhula, Sarma B. K.; Wang, Janet (2004 41st Conference Design Automation, 2004)
Keywords: Applied sciences; Circuits; Delay; Design methodology; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Fabrication; Hardware -- Hardware validation; Integrated circuits; Low power electronics; Microelectronic fabrication (materials and surfaces technology); Random variables; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Size control; Timing; Uncertainty; Yield estimation; timing yield; gate sizing; timing analysis; Performance evaluation; Monte Carlo method; Circuit design; Integrated circuit design; Algorithm; Optimization; Dimensioning; Statistical method; Microelectronic fabrication; Manufacturing process; Critical path; Numerical simulation; Delay time; CMOS integrated circuits; Deterministic approach; Random variable; Computer aided design