Advances in Embedded and Fan-Out Wafer Level Packaging Technologies

• Main Authors: Beth Keser, Steffen Kröhnert, Steffen Kroehnert
• Format: eBook
• Language: English
• Published: Newark Wiley 2019; John Wiley & Sons, Incorporated; Wiley-IEEE Press; Wiley-Blackwell
• Edition: 1
• Series: Wiley - IEEE
• Subjects: Chip scale packaging; Components, Circuits, Devices and Systems; Computing and Processing; Integrated circuits; Integrated circuits-Wafer-scale integration; microelectronic packaging research; fan-out wafer level packaging; microelectronic packaging; guide to microelectronic packaging; guide to FO-WLP; packaging technology; Advances in Embedded and Fan-Out Wafer Level Packaging Technologies; embedded technologies; embedded and fan-out wafer level packaging technologies package structure; guide to embedded technology; microelectronic packaging technology; eWLB packaging technology; the electronic packaging industry; FO-WLP technologies; embedded and fan-out wafer level packaging technologies process flows; trends in the electronic packaging industry; device packaging; FO-WLP trends; embedded packaging; FO-WLP; electronic packaging material challenges; electronic packaging; FO-WLP technology applications; embedded wafer-level ball grid array packaging technology; embedded and fan-out wafer level packaging technologies advances
• ISBN: 9781119314134; 1119314135; 9781119313984; 1119313988
• DOI: 10.1002/9781119313991

<p><b>Examines the advantages of Embedded and FO-WLP technologies, potential application spaces, package structures available in the industry, process flows, and material challenges</b> <p><i>Embedded and fan&#...

Table of Contents:

• Preface xvii List of Contributors xxiii Acknowledgments xxvii 1 History of Embedded and Fan-Out Packaging Technology 1 Michael Topper, Andreas Ostmann, Tanja Braun, and Klaus-Dieter Lang 2 FO-WLP Market and Technology Trends 39 E. Jan Vardaman 3 Embedded Wafer-Level Ball Grid Array (eWLB) Packaging Technology Platform 55 Thorsten Meyer and Steffen Krohnert 4 Ultrathin 3D FO-WLP eWLB-PoP (Embedded Wafer-Level Ball Grid Array-Package-on-Package) Technology 77 S.W. Yoon 5 NEPES’ Fan-Out Packaging Technology from Single die, SiP to Panel-Level Packaging 97 Jong Heon (Jay) Kim 6 M-Series Fan-Out with Adaptive Patterning 117 Tim Olson and Chris Scanlan 7 SWIFTR Semiconductor Packaging Technology 141 Ron Huemoeller and Curtis Zwenger 8 Embedded Silicon Fan-Out (eSiFOR) Technology for Wafer-Level System Integration 169 Daquan Yu 9 Embedding of Active and Passive Devices by Using an Embedded Interposer: The i2 Board Technology 185 Thomas Gottwald, Christian Roessle, and Alexander Neumann 10 Embedding of Power Electronic Components: The Smart p2 Pack Technology 201 Thomas Gottwald and Christian Roessle 11 Embedded Die in Substrate (Panel-Level) Packaging Technology 217 Tomoko Takahashi and Akio Katsumata 12 Blade: A Chip-First Embedded Technology for Power Packaging 241 Boris Plikat and Thorsten Scharf 13 The Role of Liquid Molding Compounds in the Success of Fan-Out Wafer-Level Packaging Technology 261 Katsushi Kan, Michiyasu Sugahara, and Markus Cichon 14 Advanced Dielectric Materials (Polyimides and Polybenzoxazoles) for Fan-Out Wafer-Level Packaging (FO-WLP) 271 T. Enomoto, J.I. Matthews, and T. Motobe 15 Enabling Low Temperature Cure Dielectrics for Advanced Wafer-Level Packaging 317 Stefan Vanclooster and Dimitri Janssen 16 The Role of Pick and Place in Fan-Out Wafer-Level Packaging 347 Hugo Pristauz, Alastair Attard, and Harald Meixner 17 Process and Equipment for eWLB: Chip Embedding by Molding 371 Edward Furgut, Hirohito Oshimori, and Hiroaki Yamagishi 18 Tools for Fan-Out Wafer-Level Package Processing 403 Nelson Fan, Eric Kuah, Eric Ng, and Otto Cheung 19 Equipment and Process for eWLB: Required PVD/Sputter Solutions 419 Chris Jones, Ricardo Gaio, and Jose Castro 20 Excimer Laser Ablation for the Patterning of Ultra-fine Routings 441 Habib Hichri, Markus Arendt, and Seongkuk Lee 21 Temporary Carrier Technologies for eWLB and RDL-First Fan-Out Wafer-Level Packages 457 Thomas Uhrmann and Boris Považay 22 Encapsulated Wafer-Level Package Technology (eWLCSP): Robust WLCSP Reliability with Sidewall Protection 471 S.W. Yoon 23 Embedded Multi-die Interconnect Bridge (EMIB): A Localized, High Density, High Bandwidth Packaging Interconnect 487 Ravi Mahajan, Robert Sankman, Kemal Aygun, Zhiguo Qian, Ashish Dhall, Jonathan Rosch, Debendra Mallik, and Islam Salama 24 Interconnection Technology Innovations in 2.5D Integrated Electronic Systems 501 Paragkumar A. Thadesar, Paul K. Jo, and Muhannad S. Bakir References 515 Index 521
• 14.12 PI-Gen2 (Negative-Acting, Solvent-Developable Material)
• 12.6.2 3D and Package on Package -- 12.7 Manufacturing Format and Scalability -- 12.8 Package Performance -- 12.8.1 Electrical Performance -- 12.8.2 Thermal Performance -- 12.8.3 Thermomechanical/CTE, Moisture, and Warpage Issues -- 12.9 Robustness and Reliability Data -- 12.9.1 First Level/Component Level (CLR) -- 12.9.2 Second-Level/Board-Level Reliability (BLR) -- 12.10 Electrical Test Considerations -- 12.11 Applications and Markets -- Acknowledgments -- References -- Chapter 13 The Role of Liquid Molding Compounds in the Success of Fan-Out Wafer-Level Packaging Technology -- 13.1 Introduction -- 13.2 The Necessity of Liquid Molding Compound for FO-WLP -- 13.3 The Required Parameters of Liquid Molding Compound for FO-WLP -- 13.4 Design of LMC Resin Formulation -- 13.5 Development of LMC in Connection with Latest Requirements -- 13.6 Current LMC Representative Proprieties -- 13.7 Conclusions -- Acknowledgment -- References -- Chapter 14 Advanced Dielectric Materials (Polyimides and Polybenzoxazoles) for Fan-Out Wafer-Level Packaging (FO-WLP) -- 14.1 Introduction -- 14.2 Brief History of PI/PBO-Based Materials in Semiconductor Applications -- 14.3 Dielectric Challenges in FO-WLP Applications -- 14.4 HDM Material Sets for FO-WLP -- 14.5 PBO-Gen3 (Positive-Acting, Aqueous-Developable Material) -- 14.6 PBO-Gen3 Process Flow -- 14.7 PBO-Gen3 Lithography -- 14.7.1 PBO-Gen3 Resolution -- 14.7.2 PBO-Gen3 Thick Film Formability -- 14.7.3 PBO-Gen3 Deep Gap Formability -- 14.8 PBO-Gen3 Material Properties -- 14.9 PBO-Gen3 Dielectric Reliability Testing -- 14.9.1 PBO-Gen3 Adhesion After PCT -- 14.9.2 PBO-Gen3 Chemical Resistance -- 14.9.3 PBO-Gen3 bHAST -- 14.10 PBO-Gen3 Package Reliability Performance (TCT Testing at Component and Board Level) -- 14.11 Performance Comparison Between PBO-Gen3 and PBO-Gen2
• 4.2 eWLB-MLP (Mold Laser Package-on-Package) Technology -- 4.2.1 Test Vehicle Specification -- 4.2.2 Assembly Process Flow -- 4.2.3 Component‐Level Reliability -- 4.2.4 Board‐Level Reliability -- 4.2.5 Failure Analysis of eWLB-MLP After Board-Level Reliability Tests -- 4.3 3D eWLB-PoP Technology -- 4.3.1 3D eWLB-PoP Test Vehicle Specification -- 4.3.2 Component-Level Reliability of 3D eWLB-PoP -- 4.3.3 Experimental Thermal Characterization of 3D eWLB-PoP -- 4.3.4 Electrical Functional Characterization of 3D eWLB-PoP -- 4.3.5 Parasitic Electrical Simulation of 3D eWLB-PoP and fcPoP -- 4.3.6 Board-Level Reliability of 3D eWLB-PoP -- 4.4 3D eWLB SiP/Module -- 4.5 Conclusions -- References -- Chapter 5 NEPES' Fan-Out Packaging Technology from Single die, SiP to Panel-Level Packaging -- 5.1 Introduction -- 5.2 Structure and Process Flow -- 5.3 Thin Fan-Out Packaging -- 5.4 Double-Sided Fan-Out Packaging -- 5.5 Via Frame (VF) Fan-Out Package -- 5.6 System-in-Package -- 5.7 Panel-Level Package -- 5.8 Performance and Reliability -- 5.8.1 Thermal Performance -- 5.8.2 Electrical Performance of Automotive Radar Package -- 5.9 Application -- 5.9.1 Mobile and Automotive Applications -- 5.9.2 Sensor Products -- 5.9.3 Optical Module -- 5.9.4 IoT and Industrial Applications -- 5.10 Roadmap and Remarks -- References -- Chapter 6 M-Series™ Fan-Out with Adaptive Patterning™ -- 6.1 Technology Description -- 6.2 Basic Package Construction -- 6.3 Manufacturing Process Flow and BOM -- 6.4 Design Features and System Integration Capability -- 6.5 Adaptive Patterning -- 6.6 Manufacturing Format and Scalability -- 6.7 Robustness and Reliability Data -- 6.8 Electrical Test Considerations -- 6.9 Applications and Markets -- Acknowledgment -- References -- Chapter 7 SWIFT® Semiconductor Packaging Technology -- 7.1 Technology Description -- 7.2 Basic Package Construction
• 7.2.1 Traditional Package-on-Package Designs -- 7.2.2 SWIFT PoP Structure -- 7.3 Manufacturing Process -- 7.4 Design Features -- 7.4.1 Form Factor -- 7.4.2 Feature Size -- 7.5 Manufacturing Format and Scalability -- 7.5.1 System in Package -- 7.5.2 Networking and High Performance Graphics (SWIFT on Substrate Applications) -- 7.6 Package Performance -- 7.6.1 Electrical Benefits -- 7.6.2 Signal and Power Integrity DDR4 (AP PoP Applications) -- 7.6.3 PCIe and Ethernet (SWIFT on Substrate Applications) -- 7.6.4 Impedance Matching -- 7.7 Thermal Performance -- 7.8 Robustness and Reliability Data -- 7.9 Applications and Markets -- References -- Chapter 8 Embedded Silicon Fan-Out (eSiFO®) Technology for Wafer-Level System Integration -- 8.1 Technology Description -- 8.2 Basic Package Construction -- 8.3 Manufacturing Process Flow -- 8.4 Design Features -- 8.5 System Integration Capability -- 8.6 Manufacturing Format and Scalability -- 8.7 Package Performance -- 8.8 Robustness and Reliability Data -- 8.9 Applications and Markets -- Acknowledgment -- References -- Chapter 9 Embedding of Active and Passive Devices by Using an Embedded Interposer: The i2 Board Technology -- 9.1 Technology Description -- 9.2 Basic Interposer Construction -- 9.3 Manufacturing Process Flow and BOM -- 9.4 Design Features -- 9.5 System Integration Capability -- 9.6 Manufacturing Format and Scalability -- 9.7 Package Performance -- 9.8 Robustness and Reliability Data -- 9.9 Electrical Test Considerations -- 9.9.1 Test Strategy -- 9.10 Applications and Markets -- 9.11 Summary -- References -- Chapter 10 Embedding of Power Electronic Components: The Smart p2 Pack Technology -- 10.1 Introduction -- 10.2 Technology Description p2 Pack -- 10.3 Basic Package Construction -- 10.4 The p2 Pack Technology Process Flow -- 10.5 Smart p2 Pack -- 10.6 Package Performance
• Intro -- Title Page -- Copyright Page -- Contents -- Preface -- List of Contributors -- Acknowledgments -- Chapter 1 History of Embedded and Fan-Out Packaging Technology -- 1.1 Introduction -- 1.2 First Embedding Technologies Based on MCM-D Concepts -- 1.2.1 GE High Density Interconnect -- 1.2.2 Fraunhofer IZM/TU Berlin -- 1.2.3 Thin Chip Integration -- 1.2.4 Irvine Sensors -- 1.2.5 3D Plus -- 1.2.6 Casio and CMK -- 1.2.7 Panel-Level Molding -- 1.3 First Embedding Technologies Based on Organic Laminates and Flex -- 1.3.1 GE Chip-on-Flex -- 1.4 Helsinki University of Technology and Imbera Electronics Embedded Chips -- 1.5 Fraunhofer IZM/TU Berlin Chip-in-Polymer (CiP) -- 1.6 HiCoFlex, Chip-in-Flex, and UTCP -- 1.7 Conclusion -- References -- Chapter 2 FO-WLP Market and Technology Trends -- 2.1 Introduction -- 2.2 FO-WLP: A Disruptive Technology -- 2.3 Embedded Die Packaging -- 2.4 FO-WLP Advantages -- 2.5 FO-WLP Versions -- 2.6 Challenges for FO-WLP -- 2.7 Drivers for FO-WLP -- 2.7.1 Markets and Applications for FO-WLP -- 2.8 Strong Demand for FO-WLP -- References -- Chapter 3 Embedded Wafer-Level Ball Grid Array (eWLB) Packaging Technology Platform -- 3.1 Technology Description -- 3.2 Basic Package Construction -- 3.2.1 Cost Performance -- 3.2.2 Electrical Performance -- 3.2.3 Interconnect Density -- 3.2.4 Thermal Performance -- 3.2.5 Board‐Level Reliability -- 3.2.6 System Integration -- 3.3 Manufacturing Process Flow and BOM -- 3.4 System Integration Capability -- 3.5 Manufacturing Format and Scalability -- 3.6 Package Performance -- 3.7 Robustness and Reliability Data -- 3.8 Electrical Test Considerations -- 3.9 Applications and Markets -- References -- Chapter 4 Ultrathin 3D FO-WLP eWLB-PoP (Embedded Wafer-Level Ball Grid Array-Package-on-Package) Technology -- 4.1 Introduction -- 4.1.1 eWLB (Embedded Wafer-Level BGA) Technology
• 10.6.1 Electrical Performance -- 10.6.2 Dynamic/Switching Losses -- 10.6.3 Inverter Efficiency -- 10.6.4 Thermal Performance -- 10.6.5 Robustness and Reliability Data -- 10.7 Applications and Markets -- 10.8 Summary -- Acknowledgments -- References -- Chapter 11 Embedded Die in Substrate (Panel-Level) Packaging Technology -- 11.1 Technology Description -- 11.2 Basic Package Construction -- 11.3 Manufacturing Process Flow and BOM -- 11.4 Design Features -- 11.5 System Integration Capability -- 11.6 Package Performance -- 11.6.1 Thermal Performance Comparison Between EDS and FBGA -- 11.6.2 Electrical Performance Comparison Among EDS, FC-BGA, and FBGA -- 11.6.3 Robustness and Reliability Data -- 11.7 Diversity of EDS Technology: Module -- 11.7.1 Technology Description -- 11.7.2 Basic Package Construction -- 11.7.3 Manufacturing Process Flow -- 11.7.4 Design Features -- 11.7.5 Robustness and Reliability Data -- 11.7.6 System Integration Capability -- 11.8 Diversity of EDS Technology: Power Devices -- 11.8.1 Technology Description -- 11.8.2 Basic Package Construction -- 11.8.3 Manufacturing Process Flow -- 11.8.4 Electrical Characteristics -- 11.8.5 Size Miniaturization and Thermal Characteristics on Power Module Package -- 11.9 Applications and Markets -- References -- Chapter 12 Blade: A Chip-First Embedded Technology for Power Packaging -- 12.1 Technology Description -- 12.2 Development and Implementation -- 12.3 Basic Package Construction -- 12.4 Manufacturing Process Flow and BOM -- 12.4.1 Manufacturing Equipment -- 12.4.2 Basic BOM -- 12.4.3 Wafer/Die/Assembly Preparation -- 12.4.4 Die Attach and Adhesion Promotion -- 12.4.5 PCB Processes -- 12.4.6 Inspection and Process Controls -- 12.5 Design Features -- 12.5.1 Mature Design Rules and Roadmap -- 12.6 System Integration Capability -- 12.6.1 2D and Side‐by‐Side Packaging