A Fast Algorithm for Transistor Folding
Transistor folding reduces the area of row-based designs that employ transistors of different size. Kim and Kang [1] have developed an O(m^2 log m) algorithm to optimally fold m transistor pairs. In this paper we develop an O(m^2) algorithm for optimal transistor folding. Our experiments indicate th...
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| Published in | VLSI Design Vol. 2001; no. 1; pp. d53 - 60 |
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| Main Authors | , |
| Format | Journal Article |
| Language | English |
| Published |
Hindawi Limiteds
01.01.2001
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| Subjects | |
| Online Access | Get full text |
| ISSN | 1065-514X 1563-5171 1026-7123 1563-5171 |
| DOI | 10.1155/2001/96353 |
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| Abstract | Transistor folding reduces the area of row-based designs that employ transistors of different size. Kim and Kang [1] have developed an O(m^2 log m) algorithm to optimally fold m transistor pairs. In this paper we develop an O(m^2) algorithm for optimal transistor folding. Our experiments indicate that our algorithm runs 3 to 60 times as fast for m values in the range (100, 100,000). |
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| AbstractList | Transistor folding reduces the area of row-based designs that employ transistors of different size. Kim and Kang [1] have developed an O(m^2 log m) algorithm to optimally fold m transistor pairs. In this paper we develop an O(m^2) algorithm for optimal transistor folding. Our experiments indicate that our algorithm runs 3 to 60 times as fast for m values in the range (100, 100,000). Transistor folding reduces the area of row‐based designs that employ transistors of different size. Kim and Kang [1] have developed an O ( m 2 log m ) algorithm to optimally fold m transistor pairs. In this paper we develop an O ( m 2 ) algorithm for optimal transistor folding. Our experiments indicate that our algorithm runs 3 to 60 times as fast for m values in the range (100, 100,000). Transistor folding reduces the area of row-based designs that employ transistors of different size. Kim and Kang [1] have developed an O(m super(2) log m) algorithm to optimally fold m transistor pairs. In this paper we develop an O(m super(2)) algorithm for optimal transistor folding. Our experiments indicate that our algorithm runs 3 to 60 times as fast for m values in the range (100, 100,000). |
| Author | EDWARD Y. C. CHENG SARTAJ SAHNI |
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| Keywords | Row-based design Transistor folding Area minimization Complexity |
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| Snippet | Transistor folding reduces the area of row-based designs that employ transistors of different size. Kim and Kang [1] have developed an O(m^2 log m) algorithm... Transistor folding reduces the area of row‐based designs that employ transistors of different size. Kim and Kang [1] have developed an O ( m 2 log m )... Transistor folding reduces the area of row-based designs that employ transistors of different size. Kim and Kang [1] have developed an O(m super(2) log m)... |
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| Title | A Fast Algorithm for Transistor Folding |
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