Allocator implementations for network-on-chip routers

• Published in: Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis pp. 1 - 12
• Main Authors: Becker, Daniel U., Dally, William J.
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 14.11.2009
• Series: ACM Conferences
• Subjects: Complexity theory; Computer systems organization > Dependable and fault-tolerant systems and networks; Computing methodologies > Modeling and simulation > Simulation evaluation; Delays; General and reference > Cross-computing tools and techniques > Performance; Hands; Hardware > Very large scale integration design > Application-specific VLSI designs > Application specific processors; Logic gates; Network topology; Networks > Network performance evaluation; Networks > Network protocols > Network layer protocols > Routing protocols; Resource management; Sensitivity; Simulation; Switches; Topology
• ISBN: 1605587443; 9781605587448
• ISSN: 2167-4329
• DOI: 10.1145/1654059.1654112

The present contribution explores the design space for virtual channel (VC) and switch allocators in network-on-chip (NoC) routers. Based on detailed RTL-level implementations, we evaluate representative allocator architectures in terms of matching quality, delay, area and power and investigate the sensitivity of these properties to key network parameters. We introduce a scheme for sparse VC allocation that limits transitions between groups of VCs based on the function they perform, and reduces the VC allocator's delay, area and power by up to 41%, 90% and 83%, respectively. Furthermore, we propose a pessimistic mechanism for speculative switch allocation that reduces switch allocator delay by up to 23% compared to a conventional implementation without increasing the router's zero-load latency. Finally, we quantify the effects of the various design choices discussed in the paper on overall network performance by presenting simulation results for two exemplary 64-node NoC topologies.