Iterative cache simulation of embedded CPUs with trace stripping

• Published in: Hardware/Software Codesign 1999: Proceedings of the IEEE 7th International Conference pp. 95 - 99
• Main Authors: Wu, Zhao, Wolf, Wayne
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 01.03.1999; IEEE
• Series: ACM Conferences
• Subjects: Acceleration; Analytical models; Computational modeling; Computing methodologies > Modeling and simulation; Costs; Embedded computing; Hardware > Integrated circuits > Semiconductor memory; Instruments; Measurement; Microprocessors; Protocols; Traffic control
• ISBN: 9781581131321; 1581131321
• ISSN: 1092-6100
• DOI: 10.1145/301177.301496

Trace-driven cache simulation is a time-consuming yet valuable procedure for evaluating the performance of embedded memory systems. In this paper we present a novel technique, called iterative cache simulation, to produce a variety of performance metrics for several different cache configurations. Compared with previous work in this field, our approach has the following features. First, it supports a wide range of performance metrics, including miss ratio, write-back counts, bus traffic, et al. Second, unlike estimation-based methods, the results produced by our simulator are accurate. Third, our approach is flexible. It can simulate both uniprocessor and multiprocessor caches, with options of higher level caches, sub-block replacement and prefetching. Last, it is fast. Our simulation results show that it has similar runtime as the fastest one-pass cache simulator.