A Generic FPGA Accelerator for Minimum Storage Regenerating Codes

• Published in: Proceedings of the ASP-DAC ... Asia and South Pacific Design Automation Conference pp. 271 - 276
• Main Authors: Qin, Mian, Lee, Joo Hwan, Pitchumani, Rekha, Ki, Yang Seok, Reddy, Narasimha, Gratz, Paul V.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.01.2020
• Subjects: Acceleration; Encoding; Field programmable gate arrays; Graphics processing units; Parallel processing; Random access memory; Throughput
• ISSN: 2153-697X
• DOI: 10.1109/ASP-DAC47756.2020.9045125

Erasure coding is widely used in storage systems to achieve fault tolerance while minimizing the storage overhead. Recently, Minimum Storage Regenerating (MSR) codes are emerging to minimize repair bandwidth while maintaining the storage efficiency. Traditionally, erasure coding is implemented in the storage software stacks, which hinders normal operations and blocks resources that could be serving other user needs due to poor cache performance and costs high CPU and memory utilizations. In this paper, we propose a generic FPGA accelerator for MSR codes encoding/decoding which maximizes the computation parallelism and minimizes the data movement between off-chip DRAM and the on-chip SRAM buffers. To demonstrate the efficiency of our proposed accelerator, we implemented the encoding/decoding algorithms for a specific MSR code called Zigzag code on Xilinx VCU1525 acceleration card. Our evaluation shows our proposed accelerator can achieve ~2.4-3.1x better throughput and ~4.2-5.7x better power efficiency compared to the state-of-art multi-core CPU implementation and ~2.8-3.3x better throughput and ~4.2-5.3x better power efficiency compared to a modern GPU accelerator.