Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement

• Published in: 2008 45th ACM/IEEE Design Automation Conference pp. 554 - 559
• Main Authors: Dong, Xiangyu, Wu, Xiaoxia, Sun, Guangyu, Xie, Yuan, Li, Helen, Chen, Yiran
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 08.06.2008; IEEE
• Series: ACM Conferences
• Subjects: 3D Stacking; CMOS logic circuits; CMOS technology; Costs; Hardware > Emerging technologies; Hardware > Very large scale integration design; Magnetic circuits; Magnetic properties; Microarchitecture; MRAM; Random access memory; Read-write memory; Semiconductor device modeling; Stacking; MRAM; 3D stacking
• ISBN: 1605581151; 9781605581156
• ISSN: 0738-100X
• DOI: 10.1145/1391469.1391610

Magnetic Random Access Memory (MRAM) has been considered as a promising memory technology due to many attractive properties. Integrating MRAM with CMOS logic may incur extra manufacture cost, due to its hybrid magnetic-CMOS fabrication process. Stacking MRAM on top of CMOS logics using 3D integration is a way to minimize this cost overhead. In this paper, we discuss the circuit design issues for MRAM, and present the MRAM cache model. Based on the model, we compare MRAM against SRAM and DRAM in terms of area, performance, and energy. Finally we conduct architectural evaluation for 3D microprocessor stacking with MRAM. The experimental results show that MRAM stacking offers competitive IPC performance with a large reduction in power consumption compared to SRAM and DRAM counterparts.