DNN Is Not All You Need: Parallelizing Non-neural ML Algorithms on Ultra-low-power IoT Processors
Machine Learning (ML) functions are becoming ubiquitous in latency- and privacy-sensitive IoT applications, prompting a shift toward near-sensor processing at the extreme edge and the consequent increasing adoption of Parallel Ultra-low-power (PULP) IoT processors. These compute- and memory-constrai...
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| Published in | ACM transactions on embedded computing systems Vol. 22; no. 3; pp. 1 - 33 |
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| Main Authors | , , |
| Format | Journal Article |
| Language | English |
| Published |
New York, NY
ACM
19.04.2023
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| Subjects | |
| Online Access | Get full text |
| ISSN | 1539-9087 1558-3465 1558-3465 |
| DOI | 10.1145/3571133 |
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| Abstract | Machine Learning (ML) functions are becoming ubiquitous in latency- and privacy-sensitive IoT applications, prompting a shift toward near-sensor processing at the extreme edge and the consequent increasing adoption of Parallel Ultra-low-power (PULP) IoT processors. These compute- and memory-constrained parallel architectures need to run efficiently a wide range of algorithms, including key Non-neural ML kernels that compete favorably with Deep Neural Networks in terms of accuracy under severe resource constraints. In this article, we focus on enabling efficient parallel execution of Non-neural ML algorithms on two RISCV-based PULP platforms, namely, GAP8, a commercial chip, and PULP-OPEN, a research platform running on an FPGA emulator. We optimized the parallel algorithms through a fine-grained analysis and intensive optimization to maximize the speedup, considering two alternative Floating-point (FP) emulation libraries on GAP8 and the native FPU support on PULP-OPEN. Experimental results show that a target-optimized emulation library can lead to an average 1.61× runtime improvement and 37% energy reduction compared to a standard emulation library, while the native FPU support reaches up to 32.09× and 99%, respectively. In terms of parallel speedup, our design improves the sequential execution by 7.04× on average on the targeted octa-core platforms leading to energy and latency decrease up to 87%. Last, we present a comparison with the ARM Cortex-M4 microcontroller, a widely adopted commercial solution for edge deployments, which is 12.87× slower than PULP-OPEN. |
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| AbstractList | Machine Learning (ML) functions are becoming ubiquitous in latency- and privacy-sensitive IoT applications, prompting a shift toward near-sensor processing at the extreme edge and the consequent increasing adoption of Parallel Ultra-low-power (PULP) IoT processors. These compute- and memory-constrained parallel architectures need to run efficiently a wide range of algorithms, including key Non-neural ML kernels that compete favorably with Deep Neural Networks in terms of accuracy under severe resource constraints. In this article, we focus on enabling efficient parallel execution of Non-neural ML algorithms on two RISCV-based PULP platforms, namely, GAP8, a commercial chip, and PULP-OPEN, a research platform running on an FPGA emulator. We optimized the parallel algorithms through a fine-grained analysis and intensive optimization to maximize the speedup, considering two alternative Floating-point (FP) emulation libraries on GAP8 and the native FPU support on PULP-OPEN. Experimental results show that a target-optimized emulation library can lead to an average 1.61× runtime improvement and 37% energy reduction compared to a standard emulation library, while the native FPU support reaches up to 32.09× and 99%, respectively. In terms of parallel speedup, our design improves the sequential execution by 7.04× on average on the targeted octa-core platforms leading to energy and latency decrease up to 87%. Last, we present a comparison with the ARM Cortex-M4 microcontroller, a widely adopted commercial solution for edge deployments, which is 12.87× slower than PULP-OPEN. |
| ArticleNumber | 56 |
| Author | Tabanelli, Enrico Tagliavini, Giuseppe Benini, Luca |
| Author_xml | – sequence: 1 givenname: Enrico orcidid: 0000-0002-3155-8774 surname: Tabanelli fullname: Tabanelli, Enrico email: enrico.tabanelli3@unibo.it organization: DEI, University of Bologna, Bologna, Italy – sequence: 2 givenname: Giuseppe orcidid: 0000-0002-9221-4633 surname: Tagliavini fullname: Tagliavini, Giuseppe email: giuseppe.tagliavini@unibo.it organization: DISI, University of Bologna, Bologna, Italy – sequence: 3 givenname: Luca orcidid: 0000-0001-8068-3806 surname: Benini fullname: Benini, Luca email: luca.benini@unibo.it organization: DEI, University of Bologna, Bologna, Italy |
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| CitedBy_id | crossref_primary_10_1109_JIOT_2023_3339254 crossref_primary_10_1109_TCAD_2022_3199903 crossref_primary_10_1007_s11042_023_16740_9 crossref_primary_10_1109_JIOT_2023_3286276 crossref_primary_10_1145_3704635 crossref_primary_10_1016_j_comnet_2023_110156 crossref_primary_10_1109_OJIES_2024_3451959 crossref_primary_10_1109_OJCOMS_2023_3323832 crossref_primary_10_1016_j_engappai_2024_109648 |
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| Title | DNN Is Not All You Need: Parallelizing Non-neural ML Algorithms on Ultra-low-power IoT Processors |
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